Command bus training for memory system
Various aspects of the present disclosure generally relate to memory devices. In some aspects, a volatile memory device may receive, from a host device, a clock (CK) signal. The memory device may receive, from the host device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern. The memory device may perform a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal. The memory device may provide, to the host device, pass or fail results associated with the CBT. Numerous other aspects are described.
1 . A volatile memory device, comprising:
one or more components configured to:
receive, from a host device, a clock (CK) signal;
receive, from the host device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern;
perform a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal; and
provide, to the host device via a first a data in or out (DQ) bus and a second DQ bus, pass or fail results associated with the CBT, wherein the pass or fail result in the first DQ bus corresponds to the CA signal latched with a rising edge of the CK signal and the pass or fail result in the second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
2 . The volatile memory device of claim 1 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits.
3 . The volatile memory device of claim 1 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
4 . The volatile memory device of claim 1 , wherein the one or more components are further configured to receive, from the host device, a chip select (CS) signal, wherein the CA signal is received when the CS signal is associated with a high value.
5 . The volatile memory device of claim 1 , wherein the volatile memory device includes a linear-feedback shift register (LFSR), and the LFSR is associated with a same predefined seed sequence as compared to an LFSR associated with the host device.
6 . The volatile memory device of claim 1 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.
7 . The volatile memory device of claim 1 , wherein the volatile memory device is associated with low-power double data rate 6 (LPDDR6).
8 . The volatile memory device of claim 1 , wherein the one or more components further configured to:
receive, from the host device, one or more additional CA signals;
perform the CBT further based on the one or more additional CA signals in relation to the CK signal; and
provide, to the host device via one or more first additional DQ buses and one or more second additional DQ buses, pass or fail results associated with the CBT.
9 . The volatile memory device of claim 8 , wherein the CBT based on the CA signals in relation to the CK signal and the CBT based on the one or more additional CA signals in relation to the CK signal are performed in parallel.
10 . The volatile memory device of claim 8 , wherein the CA signal is CA [0], the first DQ bus is DQ [0], the second DQ bus is DQ [4], the one or more additional CA signals are CA [1:3], the one ore more first additional DQ buses are DQ [1:3], and the one or more second additional DQ buses are DQ [5:7].
11 . The volatile memory device of claim 8 , wherein the pass or fail results in the one or more first additional DQ buses correspond to the one or more additional CA signals latched with the rising edge of the CK signal and the pass or fail results in the one or more second DQ buses correspond to the one or more additional CA signals latched with the falling edge of the CK signal.
12 . The volatile memory device of claim 1 , wherein the one or more components further configured to receive an entry or exit function of the CBT via a third DQ signal.
13 . A method, comprising:
receiving, by a volatile memory device and from a host device, a clock (CK) signal;
receiving, by the volatile memory device and from the host device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern;
performing, by the volatile memory device, a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal; and
providing, by the volatile memory device and to the host device via a first a data in or out (DQ) bus and a second DQ bus, pass or fail results associated with the CBT, wherein the pass or fail result in the first DQ bus corresponds to the CA signal latched with a rising edge of the CK signal and the pass or fail result in the second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
14 . The method of claim 13 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits.
15 . The method of claim 13 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
16 . The method of claim 13 , further comprising receiving, from the host device, a chip select (CS) signal, wherein the CA signal is received when the CS signal is associated with a high value.
17 . The method of claim 13 , wherein the volatile memory device includes a linear-feedback shift register (LFSR), and the LFSR is associated with a same predefined seed sequence as compared to an LFSR associated with the host device.
18 . The method of claim 13 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.
19 . The method of claim 13 , wherein the volatile memory device is associated with low-power double data rate 6 (LPDDR6).
20 . A system, comprising:
a host device configured to:
transmit a clock (CK) signal; and
transmit a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern; and
a memory device configured to:
receive the CK signal;
receive the CA signal;
perform a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal; and
provide to the host device via a first a data in or out (DQ) bus and a second DQ bus pass or fail results associated with the CBT, wherein the pass or fail result in the first DQ bus corresponds to the CA signal latched with a rising edge of the CK signal and the pass or fail result in the second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
21 . The system of claim 20 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits.
22 . The system of claim 20 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
23 . The system of claim 20 , wherein the memory device is further configured to receive a chip select (CS) signal, wherein the CA signal is received when the CS signal is associated with a high value.
24 . The system of claim 20 , wherein the memory device includes a linear-feedback shift register (LFSR), and the LFSR is associated with a same predefined seed sequence as compared to an LFSR associated with the host device.
25 . The system of claim 20 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.
26 . The system of claim 20 , wherein the memory device is associated with low-power double data rate 6 (LPDDR6).