Polar coding systems, procedures, and signaling
Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.
1. A method implemented by a wireless transmit/receive unit (WTRU), the method comprising:
generating a first plurality of uplink control information (UCI) bits to be transmitted in a first codeword;
applying a first polar code to the first UCI bits, wherein a first mother code length associated with the first polar code is determined based on a first codeword length for transmission of the first UCI bits, and wherein the first mother code length is less than the first codeword length;
performing rate matching on the first polar coded UCI bits using a repetition scheme;
transmitting the first rate matched, polar coded UCI bits;
generating a second plurality of uplink control information (UCI) bits to be transmitted in a second codeword;
applying a second polar code to the second UCI bits, wherein a second mother code length associated with the second polar code is determined based on a second codeword length for transmission of the second UCI bits, and wherein the second mother code length is greater than the second codeword length;
performing rate matching on the second polar coded UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold;
transmitting the second rate matched, polar coded UCI bits;
generating a third plurality of uplink control information (UCI) bits to be transmitted in a third codeword;
applying a third polar code to the third UCI bits, wherein a third mother code length associated with the third polar code is determined based on a third codeword length for transmission of the third UCI bits, and wherein the third mother code length is greater than the third codeword length;
performing rate matching on the third polar coded UCI bits using a shortening scheme based on a code rate for the third codeword is greater than the threshold; and
transmitting the third rate matched, polar coded UCI bits.
2. The method of claim 1 , wherein the second mother code length is determined based on the code rate for the second codeword and the third mother code length is determined based on the code rate for the third codeword.
3. The method of claim 1 , wherein the first codeword comprises a first plurality of cyclic redundancy check (CRC) bits, the second codeword comprises a second plurality of CRC bits, and the third codeword comprises a third plurality of CRC bits.
4. The method of claim 1 , wherein the code rate for the second codeword corresponds to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of coded bits in the second codeword; and
wherein the code rate for the third codeword corresponds to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of coded bits in the third codeword.
5. The method of claim 1 , wherein the first polar code comprises a first concatenated polar code, the second polar code comprises a second concatenated polar code, and the third polar code comprises a third concatenated polar code.
6. The method of claim 5 , further comprising performing the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.
7. A wireless transmit/receive unit (WTRU), comprising a processor and a memory, the processor and the memory configured to:
generate a first plurality of uplink control information (UCI) bits to be transmitted in a first codeword;
apply a first polar code to the first UCI bits, wherein a first mother code length associated with the first polar code is determined based on a first codeword length for transmission of the first UCI bits, and wherein the first mother code length is less than the first codeword length;
perform rate matching on the first polar coded UCI bits using a repetition scheme;
transmit the first rate matched, polar coded UCI bits;
generate a second plurality of uplink control information (UCI) bits to be transmitted in a second codeword;
apply a second polar code to the second UCI bits, wherein a second mother code length associated with the second polar code is determined based on a second codeword length for transmission of the second UCI bits, and wherein the second mother code length is greater than the second codeword length;
perform rate matching on the second polar coded UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold;
transmit the second rate matched, polar coded UCI bits;
generate a third plurality of uplink control information (UCI) bits to be transmitted in a third codeword;
apply a third polar code to the third UCI bits, wherein a third mother code length associated with the third polar code is determined based on a third codeword length for transmission of the third UCI bits, and wherein the third mother code length is greater than the third codeword length;
perform rate matching on the third polar coded UCI bits using a shortening scheme based on a code rate for the third codeword is greater than the threshold; and
transmit the third rate matched, polar coded UCI bits.
8. The WTRU of claim 7 , wherein the second mother code length is determined based on the code rate for the second codeword and the third mother code length is determined based on the code rate for the third codeword.
9. The WTRU of claim 7 , wherein the first codeword comprises a first plurality of cyclic redundancy check (CRC) bits, the second codeword comprises a second plurality of CRC bits, and the third codeword comprises a third plurality of CRC bits.
10. The WTRU of claim 7 , wherein the code rate for the second codeword corresponds to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of coded bits in the second codeword; and
wherein the code rate for the third codeword corresponds to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of coded bits in the third codeword.
11. The WTRU of claim 7 , wherein the first polar code comprises a first concatenated polar code, the second polar code comprises a second concatenated polar code, and the third polar code comprises a third concatenated polar code.
12. The WTRU of claim 11 , wherein the processor and the memory are further configured to:
perform the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.
13. At least one computer-readable medium having stored thereon instructions that, when executed by a processor, are configured to cause the processor to:
generate a first plurality of uplink control information (UCI) bits to be transmitted in a first codeword;
apply a first polar code to the first UCI bits, wherein a first mother code length associated with the first polar code is determined based on a first codeword length for transmission of the first UCI bits, and wherein the first mother code length is less than the first codeword length;
perform rate matching on the first polar coded UCI bits using a repetition scheme;
transmit the first rate matched, polar coded UCI bits;
generate a second plurality of uplink control information (UCI) bits to be transmitted in a second codeword;
apply a second polar code to the second UCI bits, wherein a second mother code length associated with the second polar code is determined based on a second codeword length for transmission of the second UCI bits, and wherein the second mother code length is greater than the second codeword length;
perform rate matching on the second polar coded UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold;
transmit the second rate matched, polar coded UCI bits;
generate a third plurality of uplink control information (UCI) bits to be transmitted in a third codeword;
apply a third polar code to the third UCI bits, wherein a third mother code length associated with the third polar code is determined based on a third codeword length for transmission of the third UCI bits, and wherein the third mother code length is greater than the third codeword length;
perform rate matching on the third polar coded UCI bits using a shortening scheme based on a code rate for the third codeword is greater than the threshold; and
transmit the third rate matched, polar coded UCI bits.
14. The at least one computer-readable medium of claim 13 , wherein the instructions, when executed, are further configured to cause the processor to:
determine the second mother code length based on the code rate for the second codeword; and
determine the third mother code length based on the code rate for the third codeword.
15. The at least one computer-readable medium of claim 13 , wherein the instructions, when executed, are further configured to cause the processor to:
apply a first polar code to the first UCI bits, wherein the first mother code length associated with the first polar code is determined based on a first codeword length, wherein the first codeword comprises a first plurality of cyclic redundancy check (CRC) bits;
apply a second polar code to the second UCI bits, wherein the second mother code length associated with the second polar code is determined based on the second codeword length, wherein the second codeword comprises a second plurality of CRC bits; and
apply a third polar code to the third UCI bits, wherein the third mother code length associated with the third polar code is determined based on the third codeword length, wherein the third codeword comprises a third plurality of CRC bits.
16. The at least one computer-readable medium of claim 13 , wherein the instructions, when executed, are further configured to cause the processor to:
perform rate matching on the second polar coded UCI bits, wherein the code rate for the second codeword corresponds to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of coded bits in the second codeword; and
perform rate matching on the third polar coded UCI bits, wherein the code rate for the third codeword corresponds to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of coded bits in the third codeword.
17. The at least one computer-readable medium of claim 13 , wherein the instructions, when executed, are further configured to cause the processor to:
apply a first polar code to the first UCI bits, wherein the first polar code comprises a first concatenated polar code
apply a second polar code to the second UCI bits, wherein the second polar code comprises a second concatenated polar code; and
apply a third polar code to the third UCI bits, wherein the third polar code comprises a third concatenated polar code.
18. The at least one computer-readable medium of claim 17 , wherein the instructions, when executed, are further configured to cause the processor to:
perform the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.