Methods for error count reporting with scaled error count information, and memory devices employing the same
View Patent ↗An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
1. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
perform an error control operation at the one or more memory arrays;
identify a quantity of errors associated with the one or more memory arrays based at least in part on performing the error control operation;
compare the quantity of errors to one or more threshold values; and
store, in a register associated with the one or more memory arrays, an indication that the quantity of errors satisfies the one or more threshold values.
2. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
determine a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values.
3. The memory system of claim 2 , wherein to store the indication in the register, the one or more controllers are further configured to cause the memory system to:
store the scaled value in the register.
4. The memory system of claim 2 , wherein to compare the quantity of errors to the one or more threshold values, the one or more controllers are further configured to cause the memory system to:
compare the quantity of errors to a first threshold value; and
compare the quantity of errors to a second threshold value, wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.
5. The memory system of claim 1 , wherein the error control operation comprises an error check and scrub (ECS) operation, and wherein the one or more controllers are further configured to cause the memory system to:
read, as part of the ECS operation, data associated with one or more codewords of the one or more memory arrays, wherein identifying the quantity of errors is based at least in part on identifying at least one codeword that includes data comprising one or more errors.
6. The memory system of claim 1 , wherein the one or more threshold values are stored to a second register associated with the one or more memory arrays.
7. The memory system of claim 6 , wherein the one or more threshold values are stored to the second register associated with the one or more memory arrays by a host system coupled with the memory system.
8. A method by a memory system, comprising:
performing an error control operation at one or more memory arrays of the memory system;
identifying a quantity of errors associated with the one or more memory arrays based at least in part on performing the error control operation;
comparing the quantity of errors to one or more threshold values; and
storing, in a register associated with the one or more memory arrays, an indication that the quantity of errors satisfies the one or more threshold values.
9. The method of claim 8 , further comprising:
determining a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values.
10. The method of claim 9 , wherein storing the indication in the register comprises:
storing the scaled value in the register.
11. The method of claim 9 , wherein comparing the quantity of errors to the one or more threshold values comprises:
comparing the quantity of errors to a first threshold value; and
comparing the quantity of errors to a second threshold value, wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.
12. The method of claim 8 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:
reading, as part of the ECS operation, data associated with one or more codewords of the one or more memory arrays, wherein identifying the quantity of errors is based at least in part on identifying at least one codeword that includes data comprising one or more errors.
13. The method of claim 8 , wherein the one or more threshold values are stored to a second register associated with the one or more memory arrays.
14. The method of claim 13 , wherein the one or more threshold values are stored to the second register associated with the one or more memory arrays by a host system coupled with the memory system.
15. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
perform an error control operation at one or more memory arrays of a memory system;
identify a quantity of errors associated with the one or more memory arrays based at least in part on performing the error control operation;
compare the quantity of errors to one or more threshold values; and
store, in a register associated with the one or more memory arrays, an indication that the quantity of errors satisfies the one or more threshold values.
16. The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the one or more processors to:
determine a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values.
17. The non-transitory computer-readable medium of claim 16 , wherein the instructions to store the indication in the register are executable by the one or more processors to:
store the scaled value in the register.
18. The non-transitory computer-readable medium of claim 16 , wherein the instructions to compare the quantity of errors to the one or more threshold values are executable by the one or more processors to:
compare the quantity of errors to a first threshold value; and
compare the quantity of errors to a second threshold value, wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.
19. The non-transitory computer-readable medium of claim 15 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:
reading, as part of the ECS operation, data associated with one or more codewords of the one or more memory arrays, wherein identifying the quantity of errors is based at least in part on identifying at least one codeword that includes data comprising one or more errors.
20. The non-transitory computer-readable medium of claim 15 , wherein the one or more threshold values are programmed to a second register associated with the one or more memory arrays by a manufacturer of the memory system.