Methods for error count reporting with scaled error count information, and memory devices employing the same
An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
1. An apparatus, comprising:
a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows; and
circuitry configured to:
receive, from a connected device, an indication corresponding to a threshold value;
store the indication in a threshold storage location;
perform an error detection operation on the memory array to determine a raw count of detected errors,
compare the raw count of detected errors to the threshold value to determine an over-threshold amount,
scale the over-threshold amount to determine a scaled error count, and
store the scaled error count in a user-accessible storage location.
2. The apparatus of claim 1 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of the plurality of rows and determines the raw count of detected errors based on a number of the plurality of rows that include at least one bit error.
3. The apparatus of claim 1 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of a plurality of code words stored in the memory array and determines the raw count of detected errors based on a total number of code word errors detected during the error detection operation.
4. The apparatus of claim 1 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of the plurality of rows and determines the raw count of detected errors based on one of the plurality of rows that generated a largest number of errors.
5. The apparatus of claim 1 , wherein the circuitry is configured to scale the over-threshold amount with a logarithmic scale.
6. The apparatus of claim 1 , wherein the over-threshold amount corresponds to a difference between the raw count of detected errors and the threshold value.
7. The apparatus of claim 1 , wherein the circuitry is configured to scale the over-threshold amount with a linear scale.
8. The apparatus of claim 1 , wherein the threshold value is greater than 0.
9. The apparatus of claim 1 , wherein the user-accessible storage location comprises a mode register of the apparatus.
10. The apparatus of claim 1 , wherein the memory array is a DRAM array.
11. A method comprising:
receiving, from a connected device, an indication corresponding to a threshold value;
storing the indication in a threshold storage location;
performing an error detection operation on a memory array to determine a raw count of detected errors;
comparing the raw count of detected errors to a threshold value to determine an over-threshold amount;
scaling the over-threshold amount to determine a scaled error count; and
storing the scaled error count in a user-accessible storage location.
12. The method of claim 11 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of a plurality of rows of the memory array and determines the raw count of detected errors based on a number of the plurality of rows that include at least one bit error.
13. The method of claim 11 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of a plurality of code words stored in the memory array and determines the raw count of detected errors based on a total number of code word errors detected during the error detection operation.
14. The method of claim 11 , wherein the error detection operation comprises an error check and scrub (ECS) operation that reads data from each of a plurality of rows of the memory array and determines the raw count of detected errors based on one of the plurality of rows that generated a largest number of errors.
15. The method of claim 11 , wherein scaling the over-threshold amount comprises one of a logarithmic or a linear scale.
16. An apparatus, comprising:
a memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows; and
circuitry configured to:
receive, from a connected device, a first indication corresponding to a first threshold value and a second indication corresponding to a second threshold value;
store the first indication and the second indication in a threshold storage location;
perform an error detection operation on the memory array to determine a raw count of detected errors and an initial highest detected error count,
compare the raw count of detected errors to the first threshold value to determine a first over-threshold amount,
compare the initial highest detected error count to the second threshold value to determine a second over-threshold amount,
scale the first over-threshold amount to determine a scaled total error count,
scale the second over-threshold amount to determine a scaled highest error count, and
store the scaled total error count and the scaled highest error count in a user-accessible storage location.
17. The apparatus of claim 16 , wherein the raw count of detected errors corresponds to either (i) a number of the plurality of rows that include at least one bit error, or (ii) a total number of code word errors detected during the error detection operation.
18. The apparatus of claim 16 , wherein the initial highest detected error count corresponds to one of the plurality of rows that generated a largest number of errors during the error detection operation.
19. The apparatus of claim 16 , wherein the circuitry is configured to scale the first over-threshold amount and to scale the second over-threshold amount with a logarithmic scale, a linear scale, or a combination thereof.
20. The apparatus of claim 16 , wherein the apparatus is a DDR5 DRAM device.