In-line programming adjustment of a memory cell in a memory sub-system
Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
1. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of the plurality of memory cells to be programmed to a target voltage level representing a first programming level;
causing, at a first time, first data to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level;
causing, at a second time, the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level; and
executing, in view of the second data, a level shifting operation associated with the memory cell.
2. The memory device of claim 1 , the operations further comprising causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell.
3. The memory device of claim 2 , the operations further comprising causing, in view of the first data, an inhibit voltage to be applied to a bitline corresponding to the memory cell during an application of the further programming pulse to the wordline associated with the memory cell.
4. The memory device of claim 1 , the operations further comprising performing a program verify operation corresponding to the first programming level to determine that the threshold voltage of the memory cell exceeds the target voltage level.
5. The memory device of claim 1 , the operations further comprising refreshing the cache.
6. The memory device of claim 1 , wherein the second data is stored in an additional cache.
7. The memory device of claim 1 , the operations further comprising detecting a decrease of the threshold voltage of the memory cells from a first condition where the threshold voltage exceeds the target voltage level to a second condition where the threshold voltage is less than the target voltage level, wherein the cache is refreshed in response to the detecting.
8. A method comprising:
causing a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, wherein the memory cell is to be programmed to a target voltage level representing a first programming level;
causing, at a first time, first data to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level;
causing, at a second time, the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level; and
executing, in view of the second data, a level shifting operation associated with the memory cell.
9. The method of claim 8 , further comprising causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell.
10. The method of claim 9 , further comprising causing, in view of the first data, an inhibit voltage to be applied to a bitline corresponding to the memory cell during an application of the further programming pulse to the wordline associated with the memory cell.
11. The method of claim 8 , further comprising performing a program verify operation corresponding to the first programming level to determine that the threshold voltage of the memory cell exceeds the target voltage level.
12. The method of claim 8 , further comprising refreshing the cache.
13. The method of claim 8 , further comprising:
causing one or more additional programming pulses to be applied to the wordline associated with the memory cell;
causing the cache to be refreshed to store additional data; and
terminating application of the one or more additional programming pulses in response to a determination that the additional data indicates that the threshold voltage of the memory cell exceeds the target voltage level.
14. The method of claim 8 , further comprising detecting a decrease of the threshold voltage of the memory cell from a first condition where the threshold voltage exceeds the target voltage level to a second condition where the threshold voltage is less than the target voltage level, wherein the cache is refreshed in response to the detecting.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
causing a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, wherein the memory cell is to be programmed to a target voltage level representing a first programming level;
causing, at a first time, first data to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level;
causing, at a second time, the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level; and
executing, in view of the second data, a level shifting operation associated with the memory cell.
16. The non-transitory computer-readable storage medium of claim 15 , the operations further comprising:
causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell; and
causing, in view of the first data, an inhibit voltage to be applied to a bitline corresponding to the memory cell during an application of the further programming pulse to the wordline associated with the memory cell.
17. The non-transitory computer-readable storage medium of claim 15 , the operations further comprising performing a program verify operation corresponding to the first programming level to determine that the threshold voltage of the memory cell exceeds the target voltage level.
18. The non-transitory computer-readable storage medium of claim 15 , the operations further comprising refreshing the cache.
19. The non-transitory computer-readable storage medium of claim 15 , wherein the second data is stored in an additional cache.
20. The non-transitory computer-readable storage medium of claim 15 , the operations further comprising detecting a decrease of the threshold voltage of the memory cell from a first condition where the threshold voltage exceeds the target voltage level to a second condition where the threshold voltage is less than the target voltage level, wherein the cache is refreshed in response to the detecting.