Programming delay scheme for in a memory sub-system based on memory reliability
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells. The processing device is further to determine a value of a metric reflecting reliability of a subset of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a two-pass programming operation with respect to the subset of memory cells. The two-pass programming operation includes the delay.
1 . A system comprising:
a memory device; and
a processing device operatively coupled with the memory device, the processing device to:
receive a programming command with respect to a set of memory cells of the memory device;
determine a value of a metric characterizing threshold voltage distributions of the set of memory cells;
determine a delay based on the value of the metric characterizing threshold voltage distributions;
determine, based on the value of the metric characterizing threshold voltage distributions, a subset of the set of memory cells for programming using a two-pass programming operation comprising the delay;
determine a program sequence of the two-pass programming operation based on the value of the metric characterizing threshold voltage distributions; and
perform the two-pass programming operation with respect to the subset, wherein the two-pass programming operation comprises the delay.
2 . The system of claim 1 ,
wherein the program sequence of the two-pass programming operation comprises:
a first first pass of the two-pass programming operation to be performed on a first set of sub-blocks;
a second first pass of the two-pass programming operation to be performed on a second set of sub-blocks; and
a first second pass of the two-pass programming operation to be performed on the first set of sub-blocks.
3 . The system of claim 1 , wherein determining the subset of the set of memory cells comprises determining wordlines in a wordline group corresponding to the subset of the set of memory cells.
4 . The system of claim 1 , wherein the delay is determined further based on a threshold value of the metric characterizing threshold voltage distributions.
5 . The system of claim 1 , wherein the two-pass programming operation uses one of a source to drain program sequence or a drain to source program sequence.
6 . The system of claim 1 , wherein the processing device is further to:
compare the value of the metric characterizing threshold voltage distributions to a threshold value of the metric, wherein the delay is determined based on the comparison.
7 . The system of claim 1 , wherein the delay reflects a difference between a reliability of the subset of the set of memory cells and a predetermined memory reliability threshold.
8 . The system of claim 1 , wherein the two-pass programming operation comprises the delay between a first pass of the two-pass programming operation and a second pass of the two-pass programming operation.
9 . A method, comprising:
receiving a programming command with respect to a set of memory cells;
determining a value of a metric characterizing threshold voltage distributions of the set of memory cells;
determining a delay based on the value of the metric characterizing threshold voltage distributions;
determining, based on the value of the metric characterizing threshold voltage distributions, a subset of the set of memory cells for programming using a two-pass programming operation comprising the delay;
determining a program sequence of the two-pass programming operation based on the value of the metric characterizing threshold voltage distributions; and
performing the two-pass programming operation with respect to the subset of the set of memory cells, wherein the two-pass programming operation comprises the delay.
10 . The method of claim 9 ,
wherein the program sequence of the two-pass programming operation comprises:
a first first pass of the two-pass programming operation to be performed on a first set of sub-blocks;
a second first pass of the two-pass programming operation to be performed on a second set of sub-blocks; and
a first second pass of the two-pass programming operation to be performed on the first set of sub-blocks.
11 . The method of claim 9 , wherein determining the subset of the set of memory cells comprises determining wordlines in a wordline group corresponding to the set of memory cells.
12 . The method of claim 9 , wherein the delay is determined further based on a threshold value of the metric characterizing threshold voltage distributions.
13 . The method of claim 9 , wherein the two-pass programming operation uses one of a source to drain program sequence or a drain to source program sequence.
14 . The method of claim 9 , further comprising:
comparing the value of the metric characterizing threshold voltage distributions to a threshold value, wherein the delay is determined based on the comparison.
15 . The method of claim 9 , wherein the delay reflects a difference between a reliability of the set of memory cells and a predetermined memory reliability threshold.
16 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a programming command with respect to a set of memory cells;
determine a value of a metric characterizing threshold voltage distributions of the set of memory cells;
determine a delay based on the value of the metric characterizing threshold voltage distributions;
determine, based on the value of the metric characterizing threshold voltage distributions, a subset of the set of memory cells for programming using a two-pass programming operation comprising the delay;
determine a program sequence of the two-pass programming operation based on the value of the metric characterizing threshold voltage distributions; and
perform the two-pass programming operation with respect to the subset, wherein the two-pass programming operation comprises the delay.
17 . The non-transitory computer-readable storage medium of claim 16 ,
wherein the program sequence of the two-pass programming operation comprises:
a first first pass of the two-pass programming operation to be performed on a first set of sub-blocks;
a second first pass of the two-pass programming operation to be performed on a second set of sub-blocks; and
a first second pass of the two-pass programming operation to be performed on the first set of sub-blocks.
18 . The non-transitory computer-readable storage medium of claim 16 , wherein determining the subset of the set of memory cells comprises determining wordlines in a wordline group corresponding to the subset of the set of memory cells.
19 . The non-transitory computer-readable storage medium of claim 16 , wherein the delay is determined further based on a threshold value of the metric characterizing threshold voltage distributions.
20 . The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to:
compare the value of the metric characterizing threshold voltage distributions to a threshold value, wherein the delay is determined based on the comparison.