IP Library Granted Patent US 12,463,035
Granted Patent B2
US 12,463,035 · App. 18/740,970 · Granted Nov 4, 2025

Trench etching process for photoresist line roughness improvement

Inventors: Sheng-Lin Hsieh (Hsinchu, TW); I-Chih Chen (Hsinchu, TW); Ching-Pei Hsieh (Hsinchu, TW); Kuan Jung Chen (Hsinchu, TW)
Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; TSMC NANJING COMPANY, LIMITED
H01L21/0276H01L21/0332H01L21/0337H01L21/76816H01L21/76819
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Quick Facts
Patent No.
US 12,463,035
App. No.
18/740,970
Granted
Nov 4, 2025
Kind
B2
Abstract

A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

Claims (45)

1 . A method of forming a semiconductor device structure, comprising:

forming a first resist structure over a hard mask;

patterning the first resist structure to form a trench therein;

performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench;

patterning the hard mask using the patterned resist structure as an etch mask;

forming a second resist structure over the patterned hard mask;

patterning the second resist structure to form an opening therein;

performing a second hydrogen plasma treatment to the patterned second resist structure; and

patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

2 . The method of claim 1 , wherein forming the first resist structure comprises:

depositing an organic planarization layer (OPL);

depositing an anti-reflective coating (ARC) over the OPL; and

depositing a photoresist layer over the ARC.

3 . The method of claim 1 , wherein performing the first hydrogen plasma treatment comprises reducing a line end roughness (LER) of the trench.

4 . The method of claim 1 , wherein performing the first hydrogen plasma treatment comprises reducing the LER by about 43%.

5 . The method of claim 1 , wherein patterning the first resist structure comprises forming the trench having a LER ranging from 7 nanometers (nm) to 8 nm.

6 . The method of claim 5 , wherein performing the first hydrogen plasma treatment comprises reducing the LER of the trench to about 3.8 nm to about 4.8 nm.

7 . The method of claim 1 , wherein patterning the hard mask using the patterned second resist structure comprises patterning the hard mask at a different location from the patterning the hard mask using the patterned first resist structure.

8 . The method of claim 1 , further comprising patterning a dielectric layer using the hard mask as a third etch mask.

9 . The method of claim 8 , wherein patterning the dielectric layer comprises simultaneously forming multiple openings in the dielectric layer using the hard mask as the third etch mask.

10 . The method of claim 9 , further comprising depositing a conductive material into each of the plurality of openings in the dielectric layer.

11 . A method of forming a semiconductor device structure, comprising:

patterning a first resist structure to form a trench therein, wherein the first resist structure is over a hard mask;

performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench;

forming a first opening in the hard mask using the patterned resist structure as an etch mask;

forming a second resist structure over the patterned hard mask;

patterning the second resist structure to form an opening therein;

performing a second hydrogen plasma treatment to the patterned second resist structure; and

forming a second opening in the hard mask using the patterned second resist structure as a second etch mask, wherein the second opening is offset from the first opening in a direction parallel to a top-most surface of the hard mask.

12 . The method of claim 11 , wherein performing the first hydrogen plasma treatment comprises performing the first hydrogen plasma treatment using a process gas including a fluorine-containing gas.

13 . The method of claim 11 , wherein performing the first hydrogen plasma treatment comprises performing the first hydrogen plasma treatment at a temperature ranging from about 200° C. to about 600° C.

14 . The method of claim 11 , wherein performing the first hydrogen plasma treatment comprises performing the first hydrogen plasma treatment at a pressure ranging from about 5 millitorr (mT) to about 20 mT.

15 . A method of forming a semiconductor device structure, comprising:

forming a first resist structure over a hard mask;

patterning the first resist structure to form a trench therein, wherein the trench has a first line end roughness (LER);

performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment reduces the LER of the trench by a value ranging from about 7.5 nanometers (nm) to about 7.3 nm;

patterning the hard mask using the patterned resist structure as an etch mask;

patterning a second resist structure to form an opening therein;

performing a second hydrogen plasma treatment on the patterned second resist structure; and

patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

16 . The method of claim 15 , wherein patterning the first resist structure forms the trench having the first LER less than about 8 nm.

17 . The method of claim 15 , wherein performing the first hydrogen plasma treatment comprises reducing the first LER by about 43%.

18 . The method of claim 15 , wherein performing the second hydrogen plasma treatment comprises performing the second hydrogen plasma treatment using treatment parameters equivalent to the first hydrogen plasma treatment.

19 . The method of claim 15 , wherein performing the second hydrogen plasma treatment comprises performing the second hydrogen plasma treatment having at least one treatment parameter different from the first hydrogen plasma treatment.

20 . The method of claim 15 , wherein performing the second hydrogen plasma treatment comprises reducing an LER of the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2024
From: HSIEH, SHENG-LIN; CHEN, I-CHIH; HSIEH, CHING-PEI; CHEN, KUAN JUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; TSMC NANJING COMPANY, LIMITED
Reel/Frame 067704/0736 →
Priority Claims (1)
CN 201911270313.8 · Dec 11, 2019 · national
Continuity (3)
Continuation 18054348 · Nov 10, 2022
Continuation 16742433 · Jan 14, 2020
Related Publication 20240332020A1 · Oct 3, 2024
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