IP Library Granted Patent US 12,419,169
Granted Patent B2
US 12,419,169 · App. 18/750,096 · Granted Sep 16, 2025

Display device with second initialization voltage line forming openings

Inventors: Ji Su Na (Yongin-si, KR); Won Kyu Kwak (Seongnam-si, KR); Yang Wan Kim (Hwaseong-si, KR); Young Jin Cho (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/131H10K59/353
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,419,169
App. No.
18/750,096
Granted
Sep 16, 2025
Kind
B2
Abstract

Provided is a display device which comprises a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate along a first direction, and a second initialization voltage line disposed on a different layer from the first initialization voltage line, wherein the second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along a second direction crossing the first direction, and the vertical portion may be disposed between a plurality of pixels adjacent to each other in the first direction.

Claims (59)

1. A display device comprising:

a substrate;

a plurality of pixels disposed on the substrate;

a first initialization voltage line disposed on the substrate and extending along a first direction;

a second initialization voltage line disposed on a different layer from the first initialization voltage line;

a connection electrode disposed on a same layer as the second initialization voltage line; and

a driving voltage line disposed on the second initialization voltage line and the connection electrode along the second direction,

wherein the second initialization voltage line includes horizontal portions extending along the first direction, and vertical portions extending along a second direction crossing the first direction,

the horizontal portions and the vertical portions form a plurality of opening areas each of which is completely surrounded by adjacent horizontal portions and adjacent vertical portions,

the first initialization voltage line is disposed closer to the substrate than the second initialization voltage line,

the connection electrode includes a stem portion parallel to the second direction and an extension portion extending from the stem portion in the first direction,

the extension portion of the connection electrode is not disposed in one of the plurality of pixels in which the vertical portions of the second initialization voltage line is disposed, and

each of the plurality of opening areas overlaps with at least two pixels.

2. The display device of claim 1 , wherein one vertical portion is disposed along the first direction for every two pixels.

3. The display device of claim 1 , wherein the connection electrode is connected to the driving voltage line in the extension portion of the connection electrode.

4. The display device of claim 1 ,

wherein, among pixels which are disposed adjacent each other in the first direction, one of the plurality of pixels in which the vertical portions of the second initialization voltage line is not disposed between the pixels includes extension portions being disposed at each side of the stem portion of the connection electrode, and

each of the extension portions is connected to the driving voltage line in two pixels adjacent to each other in the first direction.

5. The display device of claim 1 , further comprising:

a polycrystalline semiconductor layer disposed between the substrate and the first initialization voltage line.

6. The display device of claim 5 ,

wherein a portion of the polycrystalline semiconductor layer overlaps the connection electrode and the second initialization voltage line in a third direction perpendicular to a surface of the substrate.

7. The display device of claim 5 , further comprising:

an oxide semiconductor layer disposed between the polycrystalline semiconductor layer and the second initialization voltage line.

8. The display device of claim 7 ,

wherein the oxide semiconductor layer is disposed along the second direction, and

the oxide semiconductor layer does not overlap the polycrystalline semiconductor layer in a third direction perpendicular to the surface of the substrate.

9. The display device of claim 7 ,

wherein the oxide semiconductor layer does not overlap the connection electrode and the second initialization voltage line in a third direction perpendicular to the surface of the substrate.

10. A display device comprising:

a substrate;

a first semiconductor layer disposed on the substrate;

a first initialization voltage line extending along a first direction and disposed on the first semiconductor layer;

a second semiconductor layer disposed on the first initialization voltage line and extending along a second direction crossing the first direction;

a second initialization voltage line and a connection electrode disposed on the second semiconductor layer; and

a driving voltage line disposed on the second initialization voltage line and the connection electrode, and extending along the second direction,

wherein the second initialization voltage line includes horizontal portions extending along the first direction and vertical portions extending along the second direction,

the horizontal portions and the vertical portions form a plurality of opening areas each of which is completely surrounded by adjacent horizontal portions and adjacent vertical portions, and

the first initialization voltage line is disposed closer to the substrate than the second initialization voltage line,

the connection electrode includes a stem portion parallel to the second direction and an extension portion extending from the stem portion in the first direction,

the connection electrode is connected to the driving voltage line in the extension portion,

the extension portion of the connection electrode is not disposed in one of the plurality of pixels in which the vertical portions of the second initialization voltage line is disposed, and

each of the plurality of opening areas overlaps with at least two pixels.

11. The display device of claim 10 ,

wherein the stem portion of the connection electrode is disposed between the extension portion of the connection electrode and the vertical portions of the second initialization voltage line.

12. The display device of claim 10 ,

wherein the first semiconductor layer is a polycrystalline semiconductor layer and the second semiconductor layer is an oxide semiconductor layer, and

the first semiconductor layer and the second semiconductor layer do not overlap each other in a third direction perpendicular to a surface of the substrate.

13. The display device of claim 12 , further comprising:

a gate electrode, a first scan line, a light emission control line, and a bypass control line disposed on a same layer as the first initialization voltage line along the first direction,

wherein the polycrystalline semiconductor layer overlapping the gate electrode in the third direction perpendicular to the surface of the substrate forms a driving transistor.

14. The display device of claim 13 ,

wherein an area of the polycrystalline semiconductor layer overlapping the first scan line in the third direction perpendicular to the surface of the substrate forms a second transistor,

an area of the polycrystalline semiconductor layer overlapping the light emission control line in the third direction perpendicular to the surface of the substrate forms a fifth transistor and a sixth transistor, and

an area of the polycrystalline semiconductor layer overlapping the bypass control line in the third direction perpendicular to the surface of the substrate forms a seventh transistor and an eighth transistor.

15. The display device of claim 12 , further comprising:

an initialization control line and a second scan line disposed along the first direction between the oxide semiconductor layer and the second initialization voltage line,

wherein an area of the oxide semiconductor layer overlapping the second scan line in the third direction perpendicular to the surface of the substrate forms a third transistor, and

an area of the oxide semiconductor layer overlapping the initialization control line in the third direction perpendicular to the surface of the substrate forms a fourth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2024
From: NA, JI SU; KWAK, WON KYU; KIM, YANG WAN; CHO, YOUNG JIN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 067819/0184 →
Priority Claims (1)
KR 10-2020-0097931 · Aug 5, 2020 · national
Continuity (2)
Continuation 17326245 · May 20, 2021
Related Publication 20240349555A1 · Oct 17, 2024
References Cited (25)
US 10211275B2 · Park et al. · 2019 [cited by applicant]
US 10770533B2 · Park et al. · 2020 [cited by applicant]
US 20030160750A1 · Ueda et al. · 2003 [cited by applicant]
US 20100038739A1 · Sugio · 2010 [cited by examiner]
US 20120105785A1 · Kim et al. · 2012 [cited by applicant]
US 20120262435A1 · Park et al. · 2012 [cited by applicant]
US 20140132584A1 · Kim · 2014 [cited by applicant]
US 20140176399A1 · Lee et al. · 2014 [cited by applicant]
US 20160111487A1 · Jeong et al. · 2016 [cited by applicant]
US 20160321994A1 · Lee · 2016 [cited by examiner]
US 20170194412A1 · Park et al. · 2017 [cited by applicant]
US 20180040682A1 · Ebisuno · 2018 [cited by examiner]
US 20200005708A1 · Hwang et al. · 2020 [cited by applicant]
US 20200066212A1 · Kim et al. · 2020 [cited by applicant]
US 20200105849A1 · Kim et al. · 2020 [cited by applicant]
US 20200357877A1 · Hyun · 2020 [cited by examiner]
US 20210028258A1 · Lee et al. · 2021 [cited by applicant]
CN 105529351A · 2016 [cited by applicant]
CN 110970469A · 2020 [cited by applicant]
KR 1020160046152A · 2016 [cited by applicant]
KR 1020170028464A · 2017 [cited by applicant]
KR 1020170081105A · 2017 [cited by applicant]
KR 1020200023566A · 2020 [cited by applicant]
KR 1020200037027A · 2020 [cited by applicant]
KR 1020210049221A · 2021 [cited by applicant]