Multi-gate device and related methods
A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
1. A semiconductor device, comprising:
a first gate structure formed over a first fin in a first region of a substrate and a first source/drain feature adjacent to the first gate structure; and
a second gate structure formed over a second fin in a second region of the substrate and a second source/drain feature adjacent to the second gate structure;
wherein the first fin includes a first plurality of semiconductor channel layers interposed by a first plurality of inner spacers, the first plurality of semiconductor channel layers and the first plurality of inner spacers collectively defining a first sidewall surface;
wherein the second fin includes a second plurality of semiconductor channel layers interposed by a second plurality of inner spacers, the second plurality of semiconductor channel layers and the second plurality of inner spacers collectively defining a second sidewall surface;
wherein a first continuous adhesion layer interposes, and is in contact with, each of the first source/drain feature and the first sidewall surface; and
wherein a second continuous adhesion layer interposes, and is in contact with, each of the second source/drain feature and the second sidewall surface.
2. The semiconductor device of claim 1 , wherein the first region includes a P-type device region, and wherein the first continuous adhesion layer includes a di-borane based material.
3. The semiconductor device of claim 2 , wherein the di-borane based material includes B 2 H x or SiB 2 H x .
4. The semiconductor device of claim 1 , wherein the second region includes an N-type device region, and wherein the second continuous adhesion layer includes a di-phosphorous based material.
5. The semiconductor device of claim 4 , wherein the di-phosphorous based material includes P 2 H x or SiP 2 H x .
6. The semiconductor device of claim 1 , wherein the first region includes a P-type device type region, and wherein the first source/drain feature includes SiGe, SiB, or SiGeBx.
7. The semiconductor device of claim 1 , wherein the second region includes an N-type device type region, and wherein the second source/drain feature includes SiP, SiAs, or SiPAsx.
8. The semiconductor device of claim 1 , wherein the first source/drain feature includes a first epitaxial layer in contact with the first continuous adhesion layer and a second epitaxial layer disposed over the first epitaxial layer.
9. The semiconductor device of claim 8 , wherein the first epitaxial layer has a lower doping concentration than the second epitaxial layer.
10. The semiconductor device of claim 1 , wherein the second source/drain feature includes a third epitaxial layer in contact with the second continuous adhesion layer and a fourth epitaxial layer disposed over the third epitaxial layer.
11. The semiconductor device of claim 10 , wherein the third epitaxial layer has a lower doping concentration than the fourth epitaxial layer.
12. A semiconductor device, comprising:
a first gate structure formed over a first fin in a first region of a substrate and a first source/drain feature within a first source/drain region adjacent to the first gate structure, wherein the first source/drain feature is formed in a first trench within the first source/drain region;
wherein a first continuous adhesion layer interposes, and is in contact with, each of the first source/drain feature and a first sidewall surface of the first trench; and
wherein the first continuous adhesion layer comprises a di-borane based material including SiB 2 H x .
13. The semiconductor device of claim 12 , further comprising:
a second gate structure formed over a second fin in a second region of the substrate and a second source/drain feature within a second source/drain region adjacent to the second gate structure, wherein the second source/drain feature is formed in a second trench within the second source/drain region;
wherein a second continuous adhesion layer interposes, and is in contact with, each of the second source/drain feature and a second sidewall surface of the second trench; and
wherein the second continuous adhesion layer comprises a di-phosphorous based material including P 2 H x or SiP 2 H x .
14. The semiconductor device of claim 12 , wherein the first sidewall surface of the first trench is collectively defined by sidewall surfaces of a first plurality of semiconductor channel layers interposed by a first plurality of inner spacers.
15. The semiconductor device of claim 13 , wherein the second sidewall surface of the second trench is collectively defined by sidewall surfaces of a second plurality of semiconductor channel layers interposed by a second plurality of inner spacers.
16. The semiconductor device of claim 12 , wherein the first source/drain feature includes a first epitaxial layer in contact with the first continuous adhesion layer and a second epitaxial layer disposed over the first epitaxial layer.
17. The semiconductor device of claim 16 , wherein the first epitaxial layer has a lower doping concentration than the second epitaxial layer.
18. A semiconductor device, comprising:
a gate structure formed over a fin and a source/drain feature formed in a trench adjacent to the gate structure;
wherein an adhesion layer interposes the source/drain feature and a sidewall surface of the trench; and
wherein a portion of the source/drain feature in contact with the adhesion layer has an irregular profile.
19. The semiconductor device of claim 18 , wherein the adhesion layer includes a di-borane based material or a di-phosphorous based material.
20. The semiconductor device of claim 19 , wherein the di-borane based material includes B 2 H x or SiB 2 H x , and wherein the di-phosphorous based material includes P 2 H x or SiP 2 H x .