3-dimensional NOR memory array with very fine pitch: device and method
A NOR memory string formed by with a first conductor and a second conductor including first and second storage transistors sharing a common drain region and a common source region, the first conductor serving as gate electrode to the first storage transistor and the second conductor serving as gate electrode to the second storage transistor, each storage transistor having a channel region and a data storage layer provided between its gate electrode and its channel region, wherein the data storage layer of the first storage transistor surrounds its gate electrode, and the data storage layer of the second storage transistor does not surround its gate electrode with portions immediately adjacent the data storage layer of the first storage transistor. A dielectric barrier film between the data storage layers of the first and second storage transistors provides a discontinuity to prevent lateral conduction between the storage transistors.
1 . A NOR memory string formed by a first conductor and a second conductor, comprising first and second storage transistors sharing a common drain region and a common source region, the first conductor serving as gate electrode to the first storage transistor and the second conductor serving as gate electrode to the second storage transistor, each storage transistor having a channel region and a data storage layer provided between its gate electrode and its channel region, wherein the data storage layer of the first storage transistor surrounds its gate electrode, and the data storage layer of the second storage transistor does not surround its gate electrode and portions of the data storage layer of the second storage transistor are immediately adjacent the data storage layer of the first storage transistor; and wherein a dielectric barrier film between the data storage layer of the first storage transistor and the data storage layer of the second storage transistor provides a discontinuity to prevent lateral conduction between the first and second storage transistors.
2 . The NOR memory string of claim 1 , wherein the second conductor is adjacent a portion of the data storage layer of the first storage transistor.
3 . The NOR memory string of claim 1 , wherein the first conductor comprises a refractory metal.
4 . The NOR memory string of claim 1 , wherein the first conductor comprises a material selected from a group consisting of titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, heavily-doped p + polysilicon, heavily-doped n + polysilicon, and silicides.
5 . The NOR memory string of claim 1 , wherein the data storage layer of the first storage transistor comprises an oxide-nitride-oxide triple-layer.
6 . The NOR memory string of claim 1 , the NOR memory string is formed out of material layers of an active strip, wherein the first storage transistor and the second storage transistors are provided on opposite sides of the active strip.
7 . The NOR memory string of claim 1 , wherein the first and second storage transistors each comprise a thin-film transistor formed above a planar surface of a semiconductor substrate.
8 . The NOR memory string of claim 7 , wherein the NOR memory string is one of a plurality of NOR memory strings formed in a 3-dimensional semiconductor structure.
9 . The NOR memory string of claim 8 , wherein the semiconductor structure further comprises first and second global interconnect conductors in an insulation layer between the NOR memory string and the planar surface of the semiconductor substrate, wherein the first conductor and the second conductor are electrically connected to the first and second global interconnect conductors, respectively.
10 . The NOR memory string of claim 8 , wherein the semiconductor structure further comprises first and second global interconnect conductors in an insulation layer above the NOR memory string, wherein the first conductor and the second conductor are electrically connected to the first and second global interconnect conductors, respectively.
11 . The NOR memory string of claim 8 , wherein the semiconductor structure further comprises first and second global interconnect conductors, the first global interconnect conductor being formed in a first insulation layer above the NOR memory string and the second global interconnect being formed between the NOR memory string and the planar surface of the semiconductor substrate, wherein the first conductor is electrically connected to the first global interconnect conductor and the second conductor is electrically connected to the second global interconnect conductor.
12 . The NOR memory string of claim 11 , wherein the semiconductor structure further comprising a third global interconnection conductor formed between the NOR memory string and the planar surface of the semiconductor substrate, and wherein the third global interconnect conductor is electrically connected to the first conductor.
13 . The NOR memory string of claim 11 , wherein the semiconductor substrate comprises circuitry for supporting memory operations, and wherein the second global interconnect conductor is electrically connected to the circuitry.
14 . The NOR memory string of claim 1 , wherein the first conductor and the second conductor are electrically isolated from each other by the data storage layer of the first storage transistor.
15 . The NOR memory string of claim 1 , wherein the first conductor and the second conductor have different compositions.
16 . The NOR memory string of claim 1 , wherein at least one the first and second conductor is a metallic conductor.
17 . The NOR memory string of claim 1 , wherein the data storage layer of the first storage transistor and the data storage layer of the second storage transistor have different compositions.
18 . The NOR memory string of claim 1 , wherein the first data storage material and the second data storage material have substantially different data storage characteristics.
19 . The NOR memory string of claim 1 , wherein the data storage layer of the first storage transistor and the data storage layer of the second storage transistor are formed in two successive depositions.
20 . The NOR memory string of claim 19 , wherein the dielectric barrier film is formed as a result of the two successive depositions.