Ruthenium nucleation layer for control gate electrodes in a memory structure
A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a ruthenium portion can be formed in each backside recess, and a polycrystalline conductive material portion can be formed on each ruthenium portion. Each ruthenium portion can be employed in lieu of a tungsten seed layer to function as a lower resistivity seed layer that enables subsequent deposition of a polycrystalline conductive material. The resulting electrically conductive lines can have a lower resistivity than conductive lines of comparable dimensions that employ tungsten seed layers.
1. A three-dimensional memory device comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;
a memory opening extending through the stack; and
a memory film and a semiconductor channel located within the memory opening, wherein each of the electrically conductive layers comprises a ruthenium portion and a conductive material portion comprising a material other than ruthenium, and the ruthenium portion is more proximal to the memory film than the conductive material portion,
wherein:
a first sidewall of the ruthenium portion contacts a portion of an outer sidewall of the memory film; and
a second sidewall of the ruthenium portion contacts an inner sidewall of the conductive material portion.
2. The three-dimensional memory device of claim 1 , wherein the electrically conductive layers comprise:
a first control gate electrode located in a first device level; and
a second control gate electrode located in a second device level that is located below the first device level.
3. The three-dimensional memory device of claim 1 , wherein the first sidewall of the ruthenium portion laterally surrounds, and encloses, the memory film.
4. The three-dimensional memory device of claim 1 , wherein the conductive material portion is spaced from the insulators and the memory film by the ruthenium portion.
5. The three-dimensional memory device of claim 4 , wherein a vertical portion of the ruthenium portion has a greater thickness than horizontal portions of the ruthenium portion.
6. The three-dimensional memory device of claim 4 , wherein a vertical portion of the ruthenium portion has a same thickness as horizontal portions of the ruthenium portion.
7. The three-dimensional memory device of claim 4 , further comprising an electrically conductive liner contacting an entire bottom surface of an overlying insulator layer and an entire top surface of an underlying insulator layer.
8. The three-dimensional memory device of claim 1 , wherein each ruthenium portion is located within one level of the stack, and is disjoined from other ruthenium portions located at any other level of the stack.
9. The three-dimensional memory device of claim 1 , wherein the conductive material portion is spaced from an overlying insulator layer and is spaced from an underlying insulator layer.
10. The three-dimensional memory device of claim 1 , wherein the ruthenium portion has a uniform thickness at a vertical portion thereof, the uniform thickness being selected from a range from 3 nm to 10 nm.
11. The three-dimensional memory device of claim 1 , wherein the conductive material portion comprises tungsten.
12. The three-dimensional memory device of claim 1 , wherein the memory film comprises a stack including a blocking dielectric, at least one charge storage element, and a tunneling dielectric.
13. The three-dimensional memory device of claim 1 , wherein the conductive material portion contacts the ruthenium portion, and does not include silicon or boron therein.
14. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region; and
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.
15. The three-dimensional memory device of claim 14 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.
16. A three-dimensional memory device comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;
a memory opening extending through the stack; and
a memory film and a semiconductor channel located within the memory opening, wherein each of the electrically conductive layers comprises a ruthenium portion and a conductive material portion comprising a material other than ruthenium, and the ruthenium portion is more proximal to the memory film than the conductive material portion,
wherein:
a first sidewall of the ruthenium portion contacts a portion of an outer sidewall of the memory film; and
the first sidewall of the ruthenium portion laterally surrounds, and encloses, the memory film.
17. The three-dimensional memory device of claim 16 , wherein the electrically conductive layers comprise:
a first control gate electrode located in a first device level; and
a second control gate electrode located in a second device level that is located below the first device level.
18. The three-dimensional memory device of claim 16 , wherein a second sidewall of the ruthenium portion contacts an inner sidewall of the conductive material portion.
19. The three-dimensional memory device of claim 16 , wherein the conductive material portion is spaced from the insulators and the memory film by the ruthenium portion.
20. The three-dimensional memory device of claim 19 , wherein a vertical portion of the ruthenium portion has a greater thickness than horizontal portions of the ruthenium portion.
21. The three-dimensional memory device of claim 19 , wherein a vertical portion of the ruthenium portion has a same thickness as horizontal portions of the ruthenium portion.
22. The three-dimensional memory device of claim 19 , further comprising an electrically conductive liner contacting an entire bottom surface of an overlying insulator layer and an entire top surface of an underlying insulator layer.
23. The three-dimensional memory device of claim 16 , wherein each ruthenium portion is located within one level of the stack, and is disjoined from other ruthenium portions located at any other level of the stack.
24. The three-dimensional memory device of claim 16 , wherein the conductive material portion is spaced from an overlying insulator layer, and is spaced from an underlying insulator layer.
25. The three-dimensional memory device of claim 16 , wherein the ruthenium portion has a uniform thickness at a vertical portion thereof, the uniform thickness being selected from a range from 3 nm to 10 nm.
26. The three-dimensional memory device of claim 16 , wherein the conductive material portion comprises tungsten.
27. The three-dimensional memory device of claim 16 , wherein the memory film comprises a stack including a blocking dielectric, at least one charge storage element, and a tunneling dielectric.
28. The three-dimensional memory device of claim 16 , wherein the conductive material portion contacts the ruthenium portion, and does not include silicon or boron therein.
29. The three-dimensional memory device of claim 16 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region; and
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.
30. The three-dimensional memory device of claim 29 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.