IP Library › Granted Patent US 12,490,513
Granted Patent B2
US 12,490,513 · App. 18/767,164 · Granted Dec 2, 2025

Semiconductor device, display device, and electronic device

Inventors: Satoshi Yoshimoto (Kanagawa, JP); Koji Kusunoki (Kanagawa, JP); Kazunori Watanabe (Tokyo, JP); Susumu Kawashima (Kanagawa, JP); Marina Hiyama (Ibaraki, JP); Motoharu Saito (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D86/423G09G3/20H10D86/451H10D86/60G09G2300/0426G09G2310/0286G09G2310/0291G09G2310/08G09G2330/021
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Quick Facts
Patent No.
US 12,490,513
App. No.
18/767,164
Granted
Dec 2, 2025
Kind
B2
Abstract

A highly functional semiconductor device is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode. The first gate electrode and the second gate electrode are connected to each other, and the second electrode and the third electrode are connected to each other. A first insulating layer, a second insulating layer, and a second semiconductor layer are stacked over the first semiconductor layer. The first insulating layer is less likely to diffuse hydrogen than the second insulating layer. The second insulating layer contains oxide, the first semiconductor layer contains polycrystalline silicon, and the second semiconductor layer contains a metal oxide. The first transistor is a p-channel transistor and the second transistor is an n-channel transistor.

Claims (148)

1 . A semiconductor device comprising:

a pixel; and

a gate driver circuit, wherein the gate driver circuit comprises:

a first transistor; and

a second transistor,

wherein the first transistor is a p-channel transistor,

wherein the second transistor is an n-channel transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring to which a first potential is supplied,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first output terminal,

wherein the first output terminal is electrically connected to a first gate line,

wherein a gate of the second transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring to which a second potential is supplied,

wherein the first potential is higher than the second potential,

wherein the pixel comprises a sixth transistor, a seventh transistor, and a light-emitting element,

wherein the sixth transistor is a p-channel transistor,

wherein the seventh transistor is an n-channel transistor,

wherein the sixth transistor and the seventh transistor are electrically connected in series,

wherein one of a source and a drain of the sixth transistor is electrically connected to the light-emitting element,

wherein one of a source and a drain of the seventh transistor is electrically connected to the light-emitting element,

wherein a gate of the seventh transistor is electrically connected to the first gate line,

wherein the semiconductor device further comprises:

a first semiconductor layer over a first insulating layer;

a second insulating layer over the first semiconductor layer;

a third insulating layer over the gate of the first transistor;

a second semiconductor layer over the third insulating layer; and

a fourth insulating layer over the second semiconductor layer,

wherein the first semiconductor layer comprises polycrystalline silicon,

wherein the first semiconductor layer comprises a channel formation region of the first transistor,

wherein the gate of the first transistor is provided over the second insulating layer,

wherein the second semiconductor layer comprises a channel formation region of the second transistor,

wherein the second semiconductor layer comprises a metal oxide,

wherein the metal oxide comprises indium, and

wherein the gate of the second transistor is provided over the fourth insulating layer.

2 . The semiconductor device according to claim 1 , further comprising a fifth insulating layer over the gate of the second transistor,

wherein the fifth insulating layer is in contact with a top surface and a side surface of the gate of the second transistor, a side surface of the fourth insulating layer, and a top surface of the second semiconductor layer.

3 . The semiconductor device according to claim 1 , wherein the second semiconductor layer comprises a nanocrystal.

4 . The semiconductor device according to claim 1 ,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a fifth wiring, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the fifth wiring.

5 . A semiconductor device comprising:

a pixel; and

a gate driver circuit,

wherein the gate driver circuit comprises:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a capacitor,

wherein the first transistor is a p-channel transistor,

wherein the second transistor is an n-channel transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring to which a first potential is supplied,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first output terminal,

wherein the first output terminal is electrically connected to a first gate line,

wherein a gate of the second transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring to which a second potential is supplied,

wherein the first potential is higher than the second potential,

wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth wiring to which a clock signal is supplied,

wherein one electrode of the capacitor is electrically connected to the gate of the fourth transistor and the other of the source and the drain of the third transistor,

wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor, and a second output terminal,

wherein the second output terminal is electrically connected to a second gate line,

wherein the pixel comprises a sixth transistor, a seventh transistor, a light-emitting element, and an eighth transistor,

wherein the sixth transistor is a p-channel transistor,

wherein the seventh transistor is an n-channel transistor,

wherein the sixth transistor and the seventh transistor are electrically connected in series,

wherein one of a source and a drain of the sixth transistor is electrically connected to the light-emitting element,

wherein one of a source and a drain of the seventh transistor is electrically connected to the light-emitting element,

wherein a gate of the seventh transistor is electrically connected to the first gate line,

wherein one of a source and a drain of the eighth transistor is electrically connected to a signal line,

wherein a gate of the eighth transistor is electrically connected to the second gate line,

wherein the semiconductor device further comprises:

a first semiconductor layer over a first insulating layer;

a second insulating layer over the first semiconductor layer;

a third insulating layer over the gate of the first transistor;

a second semiconductor layer over the third insulating layer; and

a fourth insulating layer over the second semiconductor layer,

wherein the first semiconductor layer comprises polycrystalline silicon,

wherein the first semiconductor layer comprises a channel formation region of the first transistor,

wherein the gate of the first transistor is provided over the second insulating layer,

wherein the second semiconductor layer comprises a channel formation region of the second transistor,

wherein the second semiconductor layer comprises a metal oxide,

wherein the metal oxide comprises indium, and

wherein the gate of the second transistor is provided over the fourth insulating layer.

6 . The semiconductor device according to claim 5 , further comprising a fifth insulating layer over the gate of the second transistor,

wherein the fifth insulating layer is in contact with a top surface and a side surface of the gate of the second transistor, a side surface of the fourth insulating layer, and a top surface of the second semiconductor layer.

7 . The semiconductor device according to claim 5 , wherein the second semiconductor layer comprises a nanocrystal.

8 . The semiconductor device according to claim 5 ,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a fifth wiring, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the fifth wiring.

9 . A semiconductor device comprising:

a pixel; and

a gate driver circuit,

wherein the gate driver circuit comprises:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a capacitor,

wherein the first transistor is a p-channel transistor,

wherein the second transistor is an n-channel transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring to which a first potential is supplied,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first output terminal,

wherein the first output terminal is electrically connected to a first gate line,

wherein a gate of the second transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring to which a second potential is supplied,

wherein the first potential is higher than the second potential,

wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth wiring to which a clock signal is supplied,

wherein one electrode of the capacitor is electrically connected to the gate of the fourth transistor and the other of the source and the drain of the third transistor,

wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor, and a second output terminal,

wherein the second output terminal is electrically connected to a second gate line,

wherein the second transistor comprises a back gate,

wherein the back gate of the second transistor is electrically connected to the gate of the second transistor,

wherein the pixel comprises a sixth transistor, a seventh transistor, a light-emitting element, and an eighth transistor,

wherein the sixth transistor is a p-channel transistor,

wherein the seventh transistor is an n-channel transistor,

wherein the sixth transistor and the seventh transistor are electrically connected in series,

wherein one of a source and a drain of the sixth transistor is electrically connected to the light-emitting element,

wherein one of a source and a drain of the seventh transistor is electrically connected to the light-emitting element,

wherein a gate of the seventh transistor is electrically connected to the first gate line,

wherein one of a source and a drain of the eighth transistor is electrically connected to a signal line,

wherein a gate of the eighth transistor is electrically connected to the second gate line,

wherein the semiconductor device further comprises:

a first semiconductor layer over a first insulating layer;

a second insulating layer over the first semiconductor layer;

a third insulating layer over the gate of the first transistor;

a second semiconductor layer over the third insulating layer; and

a fourth insulating layer over the second semiconductor layer,

wherein the first semiconductor layer comprises polycrystalline silicon,

wherein the first semiconductor layer comprises a channel formation region of the first transistor,

wherein the gate of the first transistor is provided over the second insulating layer,

wherein the second semiconductor layer comprises a channel formation region of the second transistor,

wherein the second semiconductor layer comprises a metal oxide,

wherein the metal oxide comprises indium, and

wherein the gate of the second transistor is provided over the fourth insulating layer.

10 . The semiconductor device according to claim 9 , further comprising a fifth insulating layer over the gate of the second transistor,

wherein the fifth insulating layer is in contact with a top surface and a side surface of the gate of the second transistor, a side surface of the fourth insulating layer, and a top surface of the second semiconductor layer.

11 . The semiconductor device according to claim 9 , wherein the second semiconductor layer comprises a nanocrystal.

12 . The semiconductor device according to claim 9 ,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a fifth wiring, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the fifth wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2024
From: YOSHIMOTO, SATOSHI; KUSUNOKI, KOJI; WATANABE, KAZUNORI; KAWASHIMA, SUSUMU; HIYAMA, MARINA; SAITO, MOTOHARU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 067938/0359 →
Priority Claims (1)
JP 2020-143219 · Aug 27, 2020 · national
Continuity (2)
Continuation 18022329
Related Publication 20240379690A1 · Nov 14, 2024
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