IP Library › Granted Patent US 12,640,722
Granted Patent B2
US 12,640,722 · App. 18/768,395 · Granted May 26, 2026

Semiconductor circuit device, integrated circuit device, and inspection method

Inventor: Yoshifumi Sakamoto (Chino, JP)
Assignee: SEIKO EPSON CORPORATION
H03K17/08104
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Quick Facts
Patent No.
US 12,640,722
App. No.
18/768,395
Granted
May 26, 2026
Kind
B2
Abstract

A semiconductor circuit device includes a driver circuit, a pre-driver circuit, a first pad, first wiring, a second pad, second wiring, and a voltage clamp circuit. The driver circuit includes a high-side first transistor. The pre-driver circuit includes a first pre-driver that drives a gate of the first transistor. The first wiring couples the first pad to a source of the first transistor. The second wiring couples the second pad to a power supply node of the first pre-driver. The voltage clamp circuit clamps a voltage between power supplies of the first pre-driver.

Claims (53)

1 . A semiconductor circuit device comprising:

a driver circuit including a first transistor on a high side;

a pre-driver circuit including a first pre-driver that drives a gate of the first transistor;

a first pad;

first wiring coupling the first pad to a source of the first transistor;

a second pad;

second wiring coupling the second pad to a power supply node of the first pre-driver; and

a voltage clamp circuit that clamps a voltage between power supplies of the first pre-driver.

2 . The semiconductor circuit device according to claim 1 , wherein

the first wiring has a width larger than a width of the second wiring.

3 . The semiconductor circuit device according to claim 1 , further comprising:

third wiring coupling an output node of the first pre-driver to the gate of the first transistor, wherein

the first wiring has a width larger than a width of the third wiring.

4 . The semiconductor circuit device according to claim 1 , wherein

a breakdown voltage of a transistor included in the first pre-driver is a second breakdown voltage lower than a first breakdown voltage that is a breakdown voltage of the first transistor, and

the voltage clamp circuit receives a power supply voltage and protects the first pre-driver by clamping the power supply voltage to a voltage equal to or less than a voltage corresponding to the second breakdown voltage.

5 . The semiconductor circuit device according to claim 1 , wherein

the first transistor is a P-type transistor, and

the power supply node of the first pre-driver is a high-potential-side power supply node of the first pre-driver.

6 . The semiconductor circuit device according to claim 5 , wherein

a first voltage is supplied to the source of the first transistor, and

the first pre-driver supplies the first voltage as a high-level voltage to the gate of the first transistor and supplies, as a low-level voltage, a third voltage obtained a third voltage obtained by subtracting a second voltage lower than the first voltage to the gate of the first transistor from the first voltage.

7 . The semiconductor circuit device according to claim 1 , wherein

the first transistor is an N-type transistor, and

the power supply node of the first pre-driver is a low-potential-side power supply node of the first pre-driver.

8 . The semiconductor circuit device according to claim 7 , wherein

a fourth voltage is supplied to a drain of the first transistor,

the first pre-driver supplies, as a low-level voltage, a fifth voltage that is a voltage at the source of the first transistor to the gate of the first transistor, and

the first pre-driver supplies, as a high-level voltage, a sixth voltage obtained by adding the fifth voltage to a second voltage lower than the fourth voltage to the gate of the first transistor.

9 . The semiconductor circuit device according to claim 1 , wherein

the driver circuit includes a second transistor on a low side, and

the pre-driver circuit includes a second pre-driver circuit that drives a gate of the second transistor.

10 . The semiconductor circuit device according to claim 1 , further comprising

a third pad electrically coupled to a drain of the first transistor, wherein

a distance between the first pad and the third pad is shorter than a distance between the second pad and the third pad.

11 . An integrated circuit device comprising:

the semiconductor circuit device according to claim 1 ; and

a package housing the semiconductor circuit device, wherein

a power supply terminal of the package is electrically coupled to the first pad and the second pad.

12 . A method of inspecting a semiconductor circuit device including

a driver circuit including a first transistor on a high side,

a pre-driver circuit including a first pre-driver that drives a gate of the first transistor,

a first pad,

first wiring coupling the first pad to a source of the first transistor,

a second pad,

second wiring coupling the second pad to a power supply node of the first pre-driver, and

a voltage clamp circuit that clamps a voltage between power supplies of the first pre-driver,

the method comprising:

setting the source of the first transistor to a first inspection voltage by applying the first inspection voltage to the first pad;

setting the gate of the first transistor to a second inspection voltage different from the first inspection voltage by applying the second inspection voltage to the second pad; and

performing a screening test for a breakdown voltage between the gate and the source of the first transistor by measuring a current flowing in the first pad.

13 . The method of inspecting the semiconductor circuit device according to claim 12 , wherein

a difference between the first inspection voltage and the second inspection voltage is higher than the voltage clamped by the voltage clamp circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2024
From: SAKAMOTO, YOSHIFUMI
To: SEIKO EPSON CORPORATION
Reel/Frame 067948/0781 →
Priority Claims (1)
JP 2023-113635 · Jul 11, 2023 · national
Continuity (1)
Related Publication 20250023561A1 · Jan 16, 2025
References Cited (6)
US 6642120B2 · Terashima · 2003 [cited by examiner]
US 11710734B2 · Kono · 2023 [cited by examiner]
US 11799468B2 · Yoshimura · 2023 [cited by examiner]
JP 2005101218A · 2005 [cited by applicant]
JP 2006513585A · 2006 [cited by applicant]
WO 2004059734A1 · 2004 [cited by applicant]