SEMICONDUCTOR PACKAGE HAVING BIFACIAL SEMICONDUCTOR WAFERS

1 . A semiconductor package, comprising:

an interposer including a plurality of multiplexers (MUX) integrally formed within the interposer; and

a plurality of bifacial NAND memory devices disposed over the interposer and electrically coupled to the plurality of MUX, each of the plurality of bifacial NAND memory devices including:

a first NAND memory die disposed on a first planar surface;

a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer; and

a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die on the first planar surface with:

the second NAND memory die on the second planar surface, and

the plurality of MUX.

2 . The semiconductor package of claim 1 , wherein the plurality of bifacial NAND memory devices include:

a first bifacial NAND memory device disposed directly over the interposer, wherein the plurality of TSVs of the first bifacial NAND memory device include:

a first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device; and

a second plurality of TSVs extending through the second NAND memory die of the first bifacial NAND memory device, the second plurality of TSVs electrically coupled to:

the first NAND memory die via the first plurality of TSVs, and

the plurality of MUX; and

at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, wherein the plurality of TSVs of the at least one distinct bifacial NAND memory device includes:

a first distinct plurality of TSVs extending through the first NAND memory die of the at least one distinct bifacial NAND memory device; and

a second distinct plurality of TSVs extending through the second NAND memory die of the at least one distinct bifacial NAND memory device, the second distinct plurality of TSVs electrically coupled to:

the first distinct plurality of TSVs of the NAND memory die of the at least one distinct bifacial NAND memory device, and

the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device.

3 . The semiconductor package of claim 2 , wherein the second plurality of TSVs of the first bifacial NAND memory device is electrically coupled to the plurality of MUX by way of one of:

one or more solder bumps, or

a hybrid wafer-to-wafer bond.

4 . The semiconductor package of claim 2 , wherein the second distinct plurality of TSVs of the at least one bifacial NAND memory device is electrically coupled to the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device by one of:

one or more solder bumps, or

a hybrid wafer-to-wafer bond.

5 . The semiconductor package of claim 1 , further comprising a controller electrically coupled to the plurality of MUX and the plurality of bifacial NAND memory devices disposed over the interposer.

6 . The semiconductor package of claim 5 , wherein the controller is one of:

positioned within a recess formed in the interposer, adjacent the plurality of MUX, or

disposed on the interposer, opposite the plurality of bifacial NAND memory devices disposed over the interposer.

7 . The semiconductor package of claim 5 , wherein the controller is disposed over the plurality of bifacial NAND memory device, opposite the interposer.

8 . The semiconductor package of claim 1 , further comprising:

a distinct plurality of bifacial NAND memory devices disposed over the interposer, adjacent the plurality of bifacial NAND memory devices, each of the distinct plurality of bifacial NAND memory device including:

a first NAND memory die disposed on a first planar surface;

a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer; and

a plurality of TSVs electrically coupling the first NAND memory die on the first planar surface with:

the second NAND memory die on the second planar surface, and

the plurality of MUX;

a first redistribution layer positioned between the first NAND memory die of each of the plurality of bifacial NAND memory devices and the first NAND memory die of each of the distinct plurality of bifacial NAND memory devices, the first redistribution layer configured to enable communication between the first NAND memory die of each of the plurality of bifacial NAND memory devices and the first NAND memory die of each of the distinct plurality of bifacial NAND memory devices; and

a second redistribution layer positioned between the second NAND memory die of each of the plurality of bifacial NAND memory devices and the second NAND memory die of each of the distinct plurality of bifacial NAND memory devices, the second redistribution layer configured to enable communication between the second NAND memory die of each of the plurality of bifacial NAND memory devices and the second NAND memory die of each of the distinct plurality of bifacial NAND memory devices.

9 . An electronic device, comprising:

a printed circuit board (PCB); and

at least one semiconductor package positioned on and electrically coupled to the PCB, the at least one semiconductor package including:

an interposer disposed directly over and electrically coupled to the PCB, the interposer including a plurality of multiplexers (MUX) integrally formed within the interposer; and

a plurality of bifacial NAND memory devices disposed over the interposer and electrically coupled to the plurality of MUX and the PCB, each of the plurality of bifacial NAND memory device including:

a first NAND memory die disposed on a first planar surface;

a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer; and

a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die on the first planar surface with:

the second NAND memory die on the second planar surface, and

the plurality of MUX.

10 . The electronic device of claim 9 , wherein the plurality of bifacial NAND memory devices of the at least one semiconductor package include:

a first bifacial NAND memory device disposed directly over the interposer, wherein the plurality of TSVs of the first bifacial NAND memory device include:

a first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device; and

a second plurality of TSVs extending through the second NAND memory die of the first bifacial NAND memory device, the second plurality of TSVs electrically coupled to:

the first NAND memory die via the first plurality of TSVs, and

the plurality of MUX; and

at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, wherein the plurality of TSVs of the at least one distinct bifacial NAND memory device includes:

a first distinct plurality of TSVs extending through the first NAND memory die of the at least one distinct bifacial NAND memory device; and

a second distinct plurality of TSVs extending through the second NAND memory die of the at least one distinct bifacial NAND memory device, the second distinct plurality of TSVs electrically coupled to:

the first distinct plurality of TSVs of the NAND memory die of the at least one distinct bifacial NAND memory device, and

the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device.

11 . The electronic device of claim 10 , wherein the second plurality of TSVs of the first bifacial NAND memory device is electrically coupled to the plurality of MUX by way of one of:

one or more solder bumps, or

a hybrid wafer-to-wafer bond.

12 . The electronic device of claim 10 , wherein the second distinct plurality of TSVs of the at least one bifacial NAND memory device is electrically coupled to the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device by one of:

one or more solder bumps, or

a hybrid wafer-to-wafer bond.

13 . The electronic device of claim 9 , wherein the at least one semiconductor package further includes a controller electrically coupled to the plurality of MUX formed integrally within the interposer and the plurality of bifacial NAND memory devices disposed over the interposer.

14 . The electronic device of claim 13 , wherein the controller is one of:

positioned within a recess formed in the interposer, adjacent the plurality of MUX, or disposed on the interposer, opposite the plurality of bifacial NAND memory devices disposed over the interposer.

15 . The electronic device of claim 13 , wherein the controller is disposed over the plurality of bifacial NAND memory device, opposite the interposer.

16 . The electronic device of claim 9 , wherein the at least one semiconductor package further includes:

a distinct plurality of bifacial NAND memory devices disposed over the interposer, adjacent the plurality of bifacial NAND memory devices, each of the distinct plurality of bifacial NAND memory device including:

a first NAND memory die disposed on a first planar surface;

a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer; and

a plurality of TSVs electrically coupling the first NAND memory die on the first planar surface with:

the second NAND memory die on the second planar surface, and

the plurality of MUX;

a first redistribution layer positioned between the first NAND memory die of each of the plurality of bifacial NAND memory devices and the first NAND memory die of each of the distinct plurality of bifacial NAND memory devices, the first redistribution layer configured to enable communication between the first NAND memory die of each of the plurality of bifacial NAND memory devices and the first NAND memory die of each of the distinct plurality of bifacial NAND memory devices; and

a second redistribution layer positioned between the second NAND memory die of each of the plurality of bifacial NAND memory devices and the second NAND memory die of each of the distinct plurality of bifacial NAND memory devices, the second redistribution layer configured to enable communication between the second NAND memory die of each of the plurality of bifacial NAND memory devices and the second NAND memory die of each of the distinct plurality of bifacial NAND memory devices.

17 . The electronic device of claim 9 , wherein the interposer of the at least one semiconductor package is electrically coupled to PCB by one or more solder bumps.

18 . A semiconductor package, comprising:

an interposer including a plurality of multiplexers (MUX) integrally formed within the interposer; and

a plurality of bifacial NAND memory devices disposed over the interposer, each of the plurality of bifacial NAND memory device including:

a first NAND memory die disposed on a first planar surface;

a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer; and

means for electrically coupling the first NAND memory die on the first planar surface with:

the second NAND memory die on the second planar surface, and

the plurality of MUX.

19 . The semiconductor package of claim 18 , wherein the plurality of bifacial NAND memory devices include:

a first bifacial NAND memory device disposed directly over the interposer and including:

a first means for electrically coupling the first NAND memory die of the first bifacial NAND memory device to the second NAND memory die of the first bifacial NAND memory device; and

a second means for electrically coupling the second NAND memory die of the first bifacial NAND memory device to the plurality of MUX; and

at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, the at least one distinct bifacial NAND memory device including:

a first means for electrically coupling the first NAND memory die of the at least one distinct bifacial NAND memory device to the second NAND memory die of the at least one distinct bifacial NAND memory device; and

a second means for electrically coupling the second NAND memory die of the at least one distinct bifacial NAND memory device to the first NAND memory die of the first bifacial NAND memory device.

20 . The semiconductor package of claim 18 , further comprising a controller including means for electrically coupling the controller to the plurality of MUX and the plurality of bifacial NAND memory devices disposed over the interposer.