IP Library › Granted Patent US 12,389,660
Granted Patent B1
US 12,389,660 · App. 18/808,758 · Granted Aug 12, 2025

Semiconductor device including backside contact structure with silicide layer formed in FEOL process

Inventors: Wonkeun Chung (Clifton Park, NY); Byounghoon Kim (Rexford, NY); Jongjin Lee (Clifton Park, NY); Kang-ill Seo (Springfield, VA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D64/668H01L21/283H10D30/6729H10D62/116H10D30/014H10D30/43H10D30/6735H10D30/6757H10D62/121
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Quick Facts
Patent No.
US 12,389,660
App. No.
18/808,758
Granted
Aug 12, 2025
Kind
B1
Abstract

Provided is a semiconductor device including backside contact structure with a silicide layer formed in an FEOL process, and a method of manufacturing the same. The method includes: forming a channel structure on a substrate; forming a placeholder structure in the substrate; forming a silicide layer on the placeholder structure; forming a source/drain region on the silicide layer based on the channel structure; forming a gate structure on the channel structure; and forming a backside contact structure on a bottom surface of the placeholder structure.

Claims (30)

1. A semiconductor device comprising:

a placeholder structure;

a first silicide layer above a top surface of the placeholder structure along a first direction perpendicular to the top surface and a bottom surface of the placeholder structure;

a first source/drain region above the first silicide layer along the first direction; and

a backside contact structure below the bottom surface of the placeholder structure along the first direction,

wherein the placeholder structure is between a bottom surface of the first silicide layer and a top surface of the backside contact structure along the first direction, and

wherein each of the placeholder structure and the backside contact structure comprises a metal or a metal compound.

2. The semiconductor device of claim 1 , wherein the placeholder structure comprises a first metal.

3. The semiconductor device of claim 2 , wherein the backside contact structure comprises a second metal different from the first metal.

4. The semiconductor device of claim 1 , wherein the first silicide layer comprises nickel silicide, cobalt silicide, or titanium silicide.

5. The semiconductor device of claim 1 , further comprising a barrier metal liner on a side surface of the backside contact structure,

wherein the barrier metal liner is not formed between a side surface of the placeholder structure and a backside isolation structure.

6. The semiconductor device of claim 1 , wherein an interface, a barrier or a connection surface is formed between the placeholder structure and the backside contact structure.

7. The semiconductor device of claim 1 , further comprising a backside isolation structure surrounding the backside contact structure and the placeholder structure.

8. The semiconductor device of claim 7 , further comprising:

a supplemental isolation structure in the backside isolation structure;

a second silicide layer on a top surface of the supplemental isolation structure; and

a second source/drain region on the second silicide layer.

9. The semiconductor device of claim 8 , wherein an interface, a barrier or a connection surface is formed between the supplemental isolation structure and the backside isolation structure.

10. The semiconductor device of claim 8 , wherein the backside isolation structure comprises a first insulating material, and

wherein the supplemental isolation structure comprises the first insulating material or a second insulating material.

11. A semiconductor device comprising:

a source/drain region;

a silicide layer below a bottom surface of the source/drain region along a first direction perpendicular to the bottom surface and a bottom surface of the silicide layer;

a supplemental isolation structure below the bottom surface of the silicide layer along the first direction; and

a backside isolation structure surrounding the supplemental isolation structure,

wherein the silicide layer is between the bottom surface of the source/drain region and a top surface of the supplemental isolation structure along the first direction.

12. The semiconductor device of claim 11 , further comprising a frontside contact structure on a top surface of the source/drain region.

13. The semiconductor device of claim 11 , wherein an interface, a barrier or a connection surface is formed between the supplemental isolation structure and the backside isolation structure.

14. The semiconductor device of claim 11 , wherein the backside isolation structure comprises a first insulating material, and the supplemental isolation structure comprises the first insulating material or a second insulating material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2024
From: CHUNG, WONKEUN; KIM, BYOUNGHOON; LEE, JONGJIN; SEO, KANG-ILL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068331/0100 →
Continuity (1)
Provisional Application 63631803 · Apr 9, 2024
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