HIGH BANDWIDTH FLASH MEMORY CONTAINING A STACK OF BONDED LOGIC AND MEMORY DIE ASSEMBLIES AND METHODS FOR FORMING THE SAME
A method of forming a semiconductor includes bonding a first memory die to a first memory-controller die to form a first bonded assembly, bonding second memory die to a second memory-controller die to form a second bonded assembly, and bonding the first bonded assembly to the second bonded assembly to form a memory stack.
1 . A semiconductor structure comprising a plurality of stacked bonded assemblies, wherein:
each bonded assembly of the plurality of bonded assemblies contains a respective unit bonded assembly of a respective memory die including a respective three-dimensional array of memory elements and an array of vertical semiconductor channels, and a respective memory-controller die including a respective memory controller circuit configured to control operation of the respective three-dimensional array of memory elements; and
each vertically neighboring pair of bonded assemblies of the plurality of bonded assemblies is bonded to each other through a respective pair of arrays of bonding structures such that electrically conductive paths vertically extend from a first horizontal plane including a bottom surface of a bottommost bonded assembly of the plurality of bonded assemblies at least to a second horizontal plane including a bottom surface of a topmost bonded assembly of the plurality of bonded assemblies.
2 . The semiconductor structure of claim 1 , wherein the respective memory-controller die further comprises a semiconductor substrate and through-substrate vias which form a part of the electrically conductive paths.
3 . The semiconductor structure of claim 1 , wherein the bottom surface of a bottommost bonded assembly comprises bottom bonding structures, and a top surface of the topmost bonded assembly comprises top bonding structures.
4 . The semiconductor structure of claim 1 , wherein:
a respective one of the memory dies is present between each vertically neighboring pair of the memory-controller dies within the plurality of bonded assemblies; and
a respective one of the memory-controller dies is present between each vertically neighboring pair of the memory dies within the plurality of bonded assemblies.
5 . The semiconductor structure of claim 1 , wherein:
the respective memory die comprises respective memory-die front bonding structures embedded within respective memory-die front dielectric material layers; and
the respective memory-controller die comprises respective controller-die front bonding structures embedded within respective controller-die front dielectric material layers and bonded to the respective memory-die front bonding structures.
6 . The semiconductor structure of claim 5 , wherein the respective controller-die front bonding structures are bonded to the respective memory-die front bonding structures via metal-to-metal bonding.
7 . The semiconductor structure of claim 1 , wherein the electrically conductive paths vertically extend to a third horizontal plane including a top surface of the topmost bonded assembly of the plurality of bonded assemblies.
8 . The semiconductor structure of claim 1 , wherein:
each memory die within the plurality of bonded assemblies comprises a respective memory-die backside dielectric layer embedding respective memory-die backside bonding structures; and
each memory-controller die within the plurality of bonded assemblies comprises a respective controller-die backside dielectric layer in contact with respective controller-die backside bonding structures.
9 . The semiconductor structure of claim 8 , wherein for each vertically neighboring pair of unit bonded assemblies, memory-die backside bonding structures of the memory die of a first unit bonded assembly within said each vertically neighboring pair of unit bonded assemblies are bonded to controller-die backside bonding structures of a memory-controller die of a second unit bonded assembly within said each vertically neighboring pair of unit bonded assemblies via metal-to-metal bonding.
10 . The semiconductor structure of claim 8 , wherein for each vertically neighboring pair of unit bonded assemblies, memory-die backside bonding structures of a memory die of a first unit bonded assembly within said each vertically neighboring pair of unit bonded assemblies are bonded to controller-die backside bonding structures of a memory-controller die of a second unit bonded assembly within said each vertically neighboring pair of unit bonded assemblies through a respective array of solder material portions.
11 . The semiconductor structure of claim 10 , wherein a memory-die backside dielectric layer of the memory die of the first unit bonded assembly within said each vertically neighboring pair of unit bonded assemblies has a distal surface located within a horizontal plane including bonding surfaces of the memory-die backside bonding structures of the memory die of the first unit bonded assembly.
12 . The semiconductor structure of claim 1 , wherein each of the respective memory dies within the plurality of bonded assemblies comprises a NAND or NOR flash memory die comprising:
an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction;
a two-dimensional array of memory stack structures each containing a respective vertical semiconductor channel of the array of vertical semiconductor channels and respective vertical stack of the memory elements of the three-dimensional array of memory elements;
memory-die backside dielectric layers embedding memory-die backside metal interconnect structures;
memory-die backside bonding structures in contact with a distal memory-die backside dielectric layer among the memory-die backside dielectric layers;
through-stack via structures vertically extending at least from a horizontal plane including a bottommost surface of the alternating stack to another horizontal plane including a topmost surface of the alternating stack; and
a source connection structure electrically connected to the vertical semiconductor channels and embedded within the memory-die backside dielectric layers;
wherein a subset of the memory-die backside metal interconnect structures is located within openings in the respective source connection structure and provides electrical connection between a subset of the memory-die backside bonding structures and a subset of the through-stack via structures.
13 . The semiconductor structure of claim 1 , wherein the respective memory-controller die within each of the plurality of bonded assemblies comprises:
a respective semiconductor substrate, wherein the respective memory controller circuit comprises a respective set of semiconductor devices located on a front surface of the respective semiconductor substrate;
respective controller-die front dielectric material layers embedding respective controller-die front metal interconnect structures and located on the respective set of semiconductor devices;
a respective controller-die backside dielectric layer located on a backside surface of the respective semiconductor substrate; and
respective through-stack via structures that vertically extend through a subset of the respective controller-die front dielectric material layers, the respective semiconductor substrate, and at least a portion of the respective controller-die backside dielectric layer and in contact with a respective controller-die backside bonding structure.
14 . The semiconductor structure of claim 1 , further comprising a system level logic die that is bonded to the plurality of bonded assemblies through an array of solder material portions or through a combination of an interposer and two arrays of solder material portions.
15 . A method of forming a semiconductor structure, comprising:
bonding a first memory die to a first memory-controller die to form a first bonded assembly;
bonding second memory die to a second memory-controller die to form a second bonded assembly; and
bonding the first bonded assembly to the second bonded assembly to form a memory stack.
16 . The method of claim 15 , further comprising:
forming a plurality of memory dies on a first substrate;
forming a plurality of memory-controller dies on a second substrate;
bonding the plurality of the memory dies located on the first substrate to the plurality of the memory-controller dies located on the second substrate; and
dicing the bonded memory dies and memory-controller dies to form a plurality of the bonded assemblies, wherein the first bonded assembly comprises one of the plurality of the bonded assemblies.
17 . The method of claim 16 , further comprising forming through-substrate vias in the plurality of memory-controller dies.
18 . The method of claim 16 , wherein:
the first memory die and the second memory die comprise NAND or NOR memory dies;
the first memory die is bonded to the first memory-controller die by metal-to-metal bonding;
the second memory die is bonded to the second memory-controller die by metal-to-metal bonding;
electrically conductive paths vertically extend from a bottom surface of a bottommost bonded assembly of the memory stack to top surface of the topmost bonded assembly in the memory stack;
bottom bonding structures are located on the bottom surface of the bottommost bonded assembly of the memory stack; and
top bonding structures are located on the top surface of the topmost bonded assembly in the memory stack.
19 . The method of claim 18 , wherein the first bonded assembly is bonded to the second bonded assembly by solder material portions after the step of dicing.
20 . The method of claim 18 , wherein the first bonded assembly is bonded to the second bonded assembly by metal-to-metal bonding.