POLISHING PAD WITH IMPROVED SLURRY FLOWABILITY AND PROCESS FOR PREPARING A SEMICONDUCTOR DEVICE USING THE SAME
As specially designed second grooves in a radial form are adopted in addition to first grooves in a concentric form in the polishing pad according to an embodiment, slurry flowability can be improved, and wafer profile and polishing rate can be changed. Accordingly, the polishing pad according to the embodiment can be used in the fabrication of semiconductor devices to enhance process efficiency and product quality.
1 . A polishing pad, which comprises a polishing layer having a polishing surface, wherein the polishing layer comprises a plurality of first grooves having a circular shape and sharing the center of the polishing surface; and a plurality of second grooves formed radially from a position distanced from the center by 10% to 90% of the radius of the polishing surface to the outer periphery, and
when the silicon oxide layer of a silicon wafer is polished using a ceria slurry on the polishing surface, and when the polishing rate is measured at 30 or more random locations, the within-wafer non-uniformity (WIWNU) calculated by the following equation is 15% or less:
W
I
W
N
U
(
%
)
=
RR_stdev
RR_avg
×
1
0
0
wherein RR_stdev is the standard deviation of the polishing rate (Å/minute) measurements, and RR_avg is the average of the polishing rate (Å/minute) measurements.
2 . The polishing pad of claim 1 , wherein the WIWNU is 1% to 8%, and the RR_avg is 2,500 Å/minute to 4,000 Å/minute.
3 . The polishing pad of claim 2 , wherein the RR_avg is 3,200 Å/minute to 3,400 Å/minute.
4 . The polishing pad of claim 1 , wherein the polishing layer comprises the first grooves in a total of 50 to 150 and the second grooves in a total of 2 to 50.
5 . The polishing pad of claim 4 , wherein the width of the first groove is 0.1 mm to 1 mm, and the width of the second groove is 0.5 mm to 1.5 mm.
6 . The polishing pad of claim 5 , wherein the depth of the first groove is 0.4 mm to 1.2 mm, and the depth of the second groove is 0.5 mm to 1.5 mm.
7 . The polishing pad of claim 1 , wherein the second grooves comprise at least one of (i) to (iii) below:
(i) a plurality of second-A grooves formed radially from a position distanced from the center by 10% to 39% of the radius of the polishing surface to the outer periphery,
(ii) a plurality of second-B grooves formed radially from a position distanced from the center by 40% to 59% of the radius of the polishing surface to the outer periphery, and
(iii) a plurality of second-C grooves formed radially from a position distanced from the center by 60% to 90% of the radius of the polishing surface to the outer periphery.
8 . The polishing pad of claim 1 , which further comprises a plurality of third grooves formed radially from the center of the polishing surface to the outer periphery.
9 . The polishing pad of claim 8 , wherein the polishing layer comprises the first grooves in a total of 50 to 150, the second grooves in a total of 4 to 50, and the third grooves in a total of 4 5 to 50.
10 . A process for preparing a semiconductor device, which comprises polishing the surface of a semiconductor substrate using the polishing pad of claim 1 .