Digitally calibrated programmable clock phase generation circuit
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
1 . An integrated circuit, comprising:
a generating circuit comprising a gated ring oscillator, wherein the generating circuit is configured to provide an edge clock having a target phase within a clock period of an input clock and a having duty cycle,
wherein the generating circuit does not include a delay locked loop (DLL), and
wherein the duty cycle is other than 50/50 and the generating circuit is configured to provide the edge clock having the duty cycle by selectively turning the gated ring oscillator on and off based at least in part on a control signal.
2 . The integrated circuit of claim 1 , wherein the gated ring oscillator is configured to provide a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock.
3 . The integrated circuit of claim 2 , wherein the gated ring oscillator is configured to be programmed to adjust the first fundamental frequency within a predefined range of values.
4 . The integrated circuit of claim 2 , wherein the generating circuit comprises a control circuit configured to determine a reference count of a number of edges of the reference clock within a reference period of the reference clock.
5 . The integrated circuit of claim 4 , wherein the control circuit is configured to provide the control signal corresponding to the target phase based at least in part on a predefined sub-count of the reference count.
6 . The integrated circuit of claim 5 , wherein the predefined sub-count is programmable or adjustable.
7 . The integrated circuit of claim 5 , wherein the control circuit is configured to compute the predefined sub-count by digitally dividing the reference count by a predefined value.
8 . The integrated circuit of claim 1 , wherein the generating circuit is configured to concurrently generate multiple edge clocks having different target phases in the clock period.
9 . The integrated circuit of claim 1 , wherein the generating circuit is periodically calibrated.
10 . The integrated circuit of claim 1 , wherein the integrated circuit comprises a second generating circuit; and
wherein, when the generating circuit is calibrated, the second generating circuit is operated in a normal operating mode and, when the second generating circuit is calibrated, the generating circuit is operated in a normal operating mode.
11 . The integrated circuit of claim 1 , wherein the integrated circuit comprises an analog-to-digital converter (ADC) that is configured to use the edge clock to convert a second input signal into a quantized output.
12 . The integrated circuit of claim 11 , wherein the ADC comprises a successive-approximation-register (SAR) ADC.
13 . A system, comprising:
an integrated circuit, comprising
a generating circuit comprising a gated ring oscillator, wherein the generating circuit is configured to provide an edge clock having a target phase within a clock period of an input clock and a having duty cycle,
wherein the generating circuit does not include a delay locked loop (DLL), and
wherein the duty cycle is other than 50/50 and the generating circuit is configured to provide the edge clock having the duty cycle by selectively turning the gated ring oscillator on and off based at least in part on a control signal.
14 . The system of claim 13 , wherein the gated ring oscillator is configured to provide a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock.
15 . The system of claim 14 , wherein the generating circuit comprises a control circuit configured to determine a reference count of a number of edges of the reference clock within a reference period of the reference clock.
16 . The system of claim 13 , wherein the generating circuit is configured to concurrently generate multiple edge clocks having different target phases in the clock period.
17 . The system of claim 13 , wherein the integrated circuit comprises an analog-to-digital converter (ADC) that is configured to use the edge clock to convert a second input signal into a quantized output.
18 . A method for providing an edge clock, comprising:
by a generating circuit:
providing the edge clock having a target phase within a clock period of an input clock and having a duty cycle, wherein the generating circuit comprises a gated ring oscillator, and wherein the generating circuit does not include a delay locked loop (DLL); and
when the duty cycle is other than 50/50, providing the edge clock having the duty cycle by selectively turning the gated ring oscillator on and off based at least in part on a control signal.
19 . The method of claim 18 , wherein the providing comprises providing, using the gated ring oscillator, a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock; and
wherein the method comprises determining, using a control circuit, a reference count of a number of edges of the reference clock within a reference period of the reference clock.
20 . The method of claim 18 , wherein the generating circuit is configured to concurrently generate multiple edge clocks having different target phases in the clock period.