IP Library › Granted Patent US 11,424,736

Granted Patent B1

US 11,424,736 · App. 17/485,357 · Granted Aug 23, 2022

Adaptive clock duty-cycle controller

Inventors: Keith Alan Bowman (Morrisville, NC); Daniel Yingling (Apex, NC); Dipti Ranjan Pal (Irvine, CA)

Assignee: QUALCOMM INCORPORATED

H03K3/017 G06F1/10 H03K5/01 H03K19/20 H03K2005/00019

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Quick Facts

Patent No.: US 11,424,736
App. No.: 17/485,357
Granted: Aug 23, 2022
Kind: B1

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Abstract

Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.

Claims (120)

1. A duty-cycle adjuster, comprising:

a first multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the first multiplexer is coupled to an input of the duty-cycle adjuster;

a first inverter coupled between the input of the duty-cycle adjuster and the second input of the first multiplexer;

a phase extender having an input, and an output, wherein the input of the phase extender is coupled to the output of the first multiplexer;

a second multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the second multiplexer is coupled to the output of the phase extender, and the output of the second multiplexer is coupled to an output of the duty-cycle adjuster; and

a second inverter coupled between the output of the phase extender and the second input of the second multiplexer;

wherein the phase extender comprises:

an OR gate having a first input, a second input, and an output, wherein the first input of the OR gate is coupled to the input of the phase extender, and the output of the OR gate is coupled to the output of the phase extender; and

a delay circuit coupled between the input of the phase extender and the second input of the OR gate, wherein the delay circuit has an adjustable time delay, and the delay circuit is configured to:

receive a delay control signal at a control input of the delay circuit; and

adjust the time delay based on the received delay control signal.

2. The duty-cycle adjuster of claim 1 , wherein the phase extender comprises a high-phase extender.

3. A duty-cycle adjuster, comprising:

a first multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the first multiplexer is coupled to an input of the duty-cycle adjuster;

a first inverter coupled between the input of the duty-cycle adjuster and the second input of the first multiplexer;

a phase extender having an input, and an output, wherein the input of the phase extender is coupled to the output of the first multiplexer;

a second inverter coupled between the output of the phase extender and the second input of the second multiplexer;

wherein the phase extender comprises:

a delay circuit coupled between the input of the phase extender and the second input of the OR gate, wherein the delay circuit is configured to:

generate multiple delayed versions of a clock signal from the output of the first multiplexer, wherein each of the delayed versions of the clock signal is delayed by a different delay; and

combine high phases of the delayed versions of the clock signal into a combined clock signal.

4. The duty-cycle adjuster of claim 3 , wherein the delay circuit comprises:

delay devices coupled in series between the input of the phase extender and the second input of the OR gate;

wherein each of two or more of the delay devices has a respective first signal input, a respective second signal input, and a respective control input, wherein the respective first signal input of each of the two or more of the delay devices is coupled to a respective other one of the delay devices, and the respective second signal input of each of the two or more of the delay devices is coupled to the input of the phase extender, and wherein each of the two or more of the delay devices is configured to:

receive a respective control signal at the respective control input;

enable a respective delay output if the respective control signal has a first logic value; and

disable the respective delay output if the respective control signal has a second logic value.

5. The duty-cycle adjuster of claim 4 , wherein each of the two or more of the delay devices is configured to:

couple the respective first signal input and the respective second signal input to the respective delay output if the respective control signal has the first logic value.

6. The duty-cycle adjuster of claim 5 , wherein each of the two or more of the delay devices is configured to:

decouple the respective first signal input and the respective second signal input from the respective delay output if the respective control signal has the second logic value.

7. The duty-cycle adjuster of claim 4 , wherein each of the two or more of the delay devices comprises:

a respective OR gate having a first input, a second input, and an output, wherein the first input of the respective OR gate is coupled to the respective first signal input, and the second input of the respective OR gate is coupled to the respective second signal input; and

a respective AND gate having a first input, a second input, and an output, wherein the first input of the respective AND gate is coupled to the output of the respective OR gate, the second input of the respective AND gate is coupled to the respective control input, and the output of the respective AND gate is coupled to the respective delay output.

8. The duty-cycle adjuster of claim 7 , wherein each of the two or more of the delay devices further comprises:

one or more respective delay buffers coupled between the output of the respective AND gate and the respective delay output.

9. A duty-cycle adjuster, comprising:

a first multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the first multiplexer is coupled to an input of the duty-cycle adjuster;

a first inverter coupled between the input of the duty-cycle adjuster and the second input of the first multiplexer;

a phase extender having an input, and an output, wherein the input of the phase extender is coupled to the output of the first multiplexer;

a second inverter coupled between the output of the phase extender and the second input of the second multiplexer;

wherein the phase extender comprises:

an AND gate having a first input, a second input, and an output, wherein the first input of the AND gate is coupled to the input of the phase extender, and the output of the AND gate is coupled to the output of the phase extender; and

a delay circuit coupled between the input of the phase extender and the second input of the AND gate, wherein the delay circuit has an adjustable time delay, and the delay circuit is configured to:

receive a delay control signal at a control input of the delay circuit; and

adjust the time delay based on the received delay control signal.

10. A duty-cycle adjuster, comprising:

a first multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the first multiplexer is coupled to an input of the duty-cycle adjuster;

a first inverter coupled between the input of the duty-cycle adjuster and the second input of the first multiplexer;

a phase extender having an input, and an output, wherein the input of the phase extender is coupled to the output of the first multiplexer;

a second inverter coupled between the output of the phase extender and the second input of the second multiplexer;

wherein the phase extender comprises:

a delay circuit coupled between the input of the phase extender and the second input of the AND gate, wherein the delay circuit is configured to:

generate multiple delayed versions of a clock signal from the output of the first multiplexer, wherein each of the delayed versions of the clock signal is delayed by a different delay; and

combine low phases of the delayed versions of the clock signal into a combined clock signal.

11. The duty-cycle adjuster of claim 10 , wherein the delay circuit comprises:

delay devices coupled in series between the input of the phase extender and the second input of the AND gate;

receive a respective control signal at the respective control input;

enable a respective delay output if the respective control signal has a first logic value; and

disable the respective delay output if the respective control signal has a second logic value.

12. The duty-cycle adjuster of claim 11 , wherein each of the two or more of the delay devices is configured to:

couple the respective first signal input and the respective second signal input to the respective delay output if the respective control signal has the first logic value.

13. The duty-cycle adjuster of claim 12 , wherein each of the two or more of the delay devices is configured to:

decouple the respective first signal input and the respective second signal input from the respective delay output if the respective control signal has the second logic value.

14. The duty-cycle adjuster of claim 11 , wherein each of the two or more of the delay devices comprises:

a respective AND gate having a first input, a second input, and an output, wherein the first input of the respective AND gate is coupled to the respective first signal input, and the second input of the respective AND gate is coupled to the respective second signal input; and

a respective OR gate having a first input, a second input, and an output, wherein the first input of the respective OR gate is coupled to the output of the respective AND gate, the second input of the respective OR gate is coupled to the respective control input, and the output of the respective OR gate is coupled to the respective delay output.

15. The duty-cycle adjuster of claim 14 , wherein each of the two or more of the delay devices further comprises:

one or more respective delay buffers coupled between the output of the respective OR gate and the respective delay output.

16. A high-phase extender, comprising:

an OR gate having a first input, a second input, and an output, wherein the first input of the OR gate is coupled to an input of the high-phase extender, and the output of the OR gate is coupled to an output of the high-phase extender; and

delay devices coupled in series between the input of the high-phase extender and the second input of the OR gate;

wherein each of two or more of the delay devices has a respective first signal input, a respective second signal input, and a respective control input, wherein the respective first signal input of each of the two or more of the delay devices is coupled to a respective other one of the delay devices, and the respective second signal input of each of the two or more of the delay devices is coupled to the input of the high-phase extender, and wherein each of the two or more of the delay devices is configured to:

receive a respective control signal at the respective control input;

enable a respective delay output if the respective control signal has a first logic value; and

disable the respective delay output if the respective control signal has a second logic value.

17. The high-phase extender of claim 16 , wherein each of the two or more of the delay devices is configured to:

couple the respective first signal input and the respective second signal input to the respective delay output if the respective control signal has the first logic value.

18. The high-phase extender of claim 17 , wherein each of the two or more of the delay devices is configured to:

decouple the respective first signal input and the respective second signal input from the respective delay output if the respective control signal has the second logic value.

19. The high-phase extender of claim 16 , wherein each of the two or more of the delay devices comprises:

20. The high-phase extender of claim 19 , wherein each of the two or more of the delay devices further comprises:

one or more respective delay buffers coupled between the output of the respective AND gate and the respective delay output.

21. A low-phase extender, comprising:

an AND gate having a first input, a second input, and an output, wherein the first input of the AND gate is coupled to an input of the low-phase extender, and the output of the AND gate is coupled to an output of the low-phase extender; and

delay devices coupled in series between the input of the low-phase extender and the second input of the AND gate;

wherein each of two or more of the delay devices has a respective first signal input, a respective second signal input, and a respective control input, wherein the respective first signal input of each of the two or more of the delay devices is coupled to a respective other one of the delay devices, and the respective second signal input of each of the two or more of the delay devices is coupled to the input of the low-phase extender, and wherein each of the two or more of the delay devices is configured to:

receive a respective control signal at the respective control input;

enable a respective delay output if the respective control signal has a first logic value; and

disable the respective delay output if the respective control signal has a second logic value.

22. The low-phase extender of claim 21 , wherein each of the two or more of the delay devices is configured to:

couple the respective first signal input and the respective second signal input to the respective delay output if the respective control signal has the first logic value.

23. The low-phase extender of claim 22 , wherein each of the two or more of the delay devices is configured to:

decouple the respective first signal input and the respective second signal input from the respective delay output if the respective control signal has the second logic value.

24. The low-phase extender of claim 21 , wherein each of the two or more of the delay devices comprises:

25. The low-phase extender of claim 24 , wherein each of the two or more of the delay devices further comprises:

one or more respective delay buffers coupled between the output of the respective OR gate and the respective delay output.

26. A method of phase extension using a delay circuit including delay devices coupled in series, comprising:

receiving a clock signal;

generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices; and

combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.

27. The method of claim 26 , further comprising:

performing an OR operation on the received clock signal and the combined clock signal.

28. The method of claim 26 , further comprising:

performing an AND operation on the received clock signal and the combined clock signal.

29. The method of claim 26 , wherein generating the multiple delayed versions of the clock signal comprises propagating the clock signal through a different number of the delay devices for each of the multiple delayed versions of the clock signal.

30. The method of claim 26 , wherein a first one of the delayed versions of the clock signal is delayed by one of the delay devices, and a second one of the delayed versions of the clock signal is delayed by two of the delay devices.

31. The method of claim 29 , wherein propagating the clock signal through a different number of the delay devices for each of the multiple delayed versions of the clock signal comprises:

propagating the clock signal through one of the delay devices for a first one of the delayed versions of the clock signal; and

propagating the clock signal through two of the delay devices for a second one of the delayed versions of the clock signal.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2022

From: BOWMAN, KEITH ALAN; YINGLING, DANIEL; PAL, DIPTI RANJAN

To: QUALCOMM INCORPORATED

Reel/Frame 059868/0891 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021

From: BOWMAN, KEITH ALAN; YINGLING, DANIEL; PAL, DIPTI RANJAN

To: QUALCOMM INCORPORATED

Reel/Frame 057786/0045 →

Cited By (3)

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