Clock quality measurements and monitoring in 5G network
An apparatus configured to perform clock quality measurements and monitoring operations in one or more communication networks may comprise a memory and a processor communicatively coupled to one another. The processor may be configured to receive a first clock and a second clock from a network device, obtain multiple thresholds associated with the network device, obtain multiple error detection configuration commands, select a threshold of the multiple thresholds, select an error detection configuration command, and evaluate the first clock based at least in part upon the threshold and the error detection configuration command. Further, the processor may be configured to generate a result indicating whether the first clock comprises a clock error greater than the threshold and record the threshold and the error detection configuration command against an input reference of the clock in response to generating the result indicating that the clock comprises the clock error greater than the threshold.
1 . An apparatus, comprising:
a memory configured to store:
a plurality of clock source selection operations configured to facilitate selection of one or more clock sources; and
a plurality of clock monitoring operations configured to monitor the plurality of clock source selection operations; and
a processor communicatively coupled to the memory and configured to:
receive a first clock and a second clock from a first network device;
obtain a plurality of thresholds associated with the first network device;
obtain a plurality of error detection configuration commands, each error detection configuration command of the plurality of error detection configuration commands is configured to evaluate clock errors in the first clock;
in accordance with the plurality of clock monitoring operations, select a first threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select a first error detection configuration command of the plurality of error detection configuration commands;
evaluate the first clock based at least in part upon the first threshold and the first error detection configuration command;
generate a first result indicating whether the first clock comprises a first clock error greater than the first threshold; and
in response to generating the first result indicating that the first clock comprises the first clock error greater than the first threshold, record the first threshold and the first error detection configuration command against a first input reference of the first clock.
2 . The apparatus of claim 1 , wherein the processor is further configured to:
in accordance with the plurality of clock monitoring operations, select a second threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select a second error detection configuration command of the plurality of error detection configuration commands;
evaluate the second clock based at least in part upon the second threshold and the second error detection configuration command; and
generate a second result indicating whether the second clock comprises a second clock error greater than the second threshold.
3 . The apparatus of claim 2 , wherein the processor is further configured to:
in response to generating the second result indicating that the second clock comprises the second clock error greater than the second threshold, record the second threshold and the second error detection configuration command against a second input reference of the first clock;
select a third threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select the second error detection configuration command of the plurality of error detection configuration commands;
evaluate the first clock based at least in part upon the third threshold and the second error detection configuration command; and
generate a third result indicating whether the first clock comprises a third clock error greater than the third threshold.
4 . The apparatus of claim 3 , wherein the second threshold is lower than the third threshold.
5 . The apparatus of claim 1 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Precise Frequency Monitor (PFM).
6 . The apparatus of claim 1 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Single Cycle Monitor (SCM).
7 . The apparatus of claim 1 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Coarse Frequency Monitor (CFM).
8 . A method, comprising:
receiving a first clock and a second clock from a first network device;
obtaining a plurality of thresholds associated with the first network device;
obtaining a plurality of error detection configuration commands, each error detection configuration command of the plurality of error detection configuration commands is configured to evaluate clock errors in the first clock;
in accordance with a plurality of clock monitoring operations, selecting a first threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, selecting a first error detection configuration command of the plurality of error detection configuration commands;
evaluating the first clock based at least in part upon the first threshold and the first error detection configuration command;
generating a first result indicating whether the first clock comprises a first clock error greater than the first threshold; and
in response to generating the first result indicating that the first clock comprises the first clock error greater than the first threshold, recording the first threshold and the first error detection configuration command against a first input reference of the first clock.
9 . The method of claim 8 , further comprising:
in accordance with the plurality of clock monitoring operations, selecting a second threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, selecting a second error detection configuration command of the plurality of error detection configuration commands;
evaluating the second clock based at least in part upon the second threshold and the second error detection configuration command; and
generating a second result indicating whether the second clock comprises a second clock error greater than the second threshold.
10 . The method of claim 9 , further comprising:
in response to generating the second result indicating that the second clock comprises the second clock error greater than the second threshold, recording the second threshold and the second error detection configuration command against a second input reference of the first clock;
selecting a third threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, selecting the second error detection configuration command of the plurality of error detection configuration commands;
evaluating the first clock based at least in part upon the third threshold and the second error detection configuration command; and
generating a third result indicating whether the first clock comprises a third clock error greater than the third threshold.
11 . The method of claim 10 , wherein the second threshold is lower than the third threshold.
12 . The method of claim 8 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Precise Frequency Monitor (PFM).
13 . The method of claim 8 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Single Cycle Monitor (SCM).
14 . The method of claim 8 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Coarse Frequency Monitor (CFM).
15 . A non-transitory computer readable medium storing instructions that when executed by a processor cause the processor to:
receive a first clock and a second clock from a first network device;
obtain a plurality of thresholds associated with the first network device;
obtain a plurality of error detection configuration commands, each error detection configuration command of the plurality of error detection configuration commands is configured to evaluate clock errors in the first clock;
in accordance with a plurality of clock monitoring operations, select a first threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select a first error detection configuration command of the plurality of error detection configuration commands;
evaluate the first clock based at least in part upon the first threshold and the first error detection configuration command;
generate a first result indicating whether the first clock comprises a first clock error greater than the first threshold; and
in response to generating the first result indicating that the first clock comprises the first clock error greater than the first threshold, record the first threshold and the first error detection configuration command against a first input reference of the first clock.
16 . The non-transitory computer readable medium of claim 15 , wherein the processor is further caused to:
in accordance with the plurality of clock monitoring operations, select a second threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select a second error detection configuration command of the plurality of error detection configuration commands;
evaluate the second clock based at least in part upon the second threshold and the second error detection configuration command; and
generate a second result indicating whether the second clock comprises a second clock error greater than the second threshold.
17 . The non-transitory computer readable medium of claim 16 , wherein the processor is further caused to:
in response to generating the second result indicating that the second clock comprises the second clock error greater than the second threshold, record the second threshold and the second error detection configuration command against a second input reference of the first clock;
select a third threshold of the plurality of thresholds;
in accordance with the plurality of clock monitoring operations, select the second error detection configuration command of the plurality of error detection configuration commands;
evaluate the first clock based at least in part upon the third threshold and the second error detection configuration command; and
generate a third result indicating whether the first clock comprises a third clock error greater than the third threshold.
18 . The non-transitory computer readable medium of claim 15 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Precise Frequency Monitor (PFM).
19 . The non-transitory computer readable medium of claim 15 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Single Cycle Monitor (SCM).
20 . The non-transitory computer readable medium of claim 15 , wherein the plurality of clock monitoring operations are at least partially performed in accordance with one or more configuration commands associated with a Coarse Frequency Monitor (CFM).