Clock synchronization loop

1. A synchronized communication system, comprising:

a plurality of compute nodes including a first compute node, one or more intermediate compute nodes, and a last compute node; and

clock connections to connect the compute nodes in a closed loop configuration, wherein:

each of the compute nodes has an output connected to an input of a next one of the compute nodes via a respective one of the clock connections, while the last compute node has an output connected to an input of the first compute node via another respective one of the clock connections;

the compute nodes are configured to distribute among the compute nodes, via ones of the clock connections, a master clock frequency from any selected one of the compute nodes, which is designated as a master clock;

at a first time one of the plurality of compute nodes is designated as the master clock and is configured to distribute the master clock frequency among the compute nodes; and

at a second time another one of the plurality of compute nodes is designated as the master clock, and is configured to distribute the master clock frequency among the compute nodes.

2. The system according to claim 1 , further comprising a controller to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.

3. The system according to claim 1 , wherein the compute nodes include at least one of the following: a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.

4. The system according to claim 1 , wherein each of the compute nodes comprises:

one or more ports to transmit and receive respective communication signals over respective network links; and

clock synchronization circuitry to process at least one of the respective communication signals received by the one or more ports so as to recover a respective remote clock.

5. The system according to claim 1 , wherein the first compute node comprises:

clock synchronization circuitry to recover a remote clock;

a clock input port connected to a clock output port of a third compute node of the plurality of compute nodes via a first one of the clock connections, and configured to receive a clock signal at the master clock frequency from the third compute node; and

a clock output port connected to a clock input port of a second compute node of the plurality of compute nodes via a second one of the clock connections.

6. The system according to claim 5 , wherein the third compute node and the second compute node are a same one of the compute nodes.

7. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:

discipline a local clock signal to the master clock frequency responsively to: the recovered respective remote clock; or the received clock signal; and

output the disciplined local clock signal via the clock output port to the second compute node.

8. The system according to claim 7 , wherein the clock synchronization circuitry comprises a frequency synthesizer.

9. The system according to claim 8 , wherein the frequency synthesizer is a frequency jitter synchronizer.

10. The system according to claim 8 , wherein the frequency synthesizer is a jitter network synchronizer clock.

11. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:

discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock; and

output the disciplined local clock signal via the clock output port to the second compute node.

12. The system according to claim 11 , wherein the clock synchronization circuitry is configured to ignore the clock signal received by the clock input port.

13. The system according to claim 12 , further comprising a controller to selectively block distribution of the master clock frequency in the closed loop by instructing the clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.

14. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:

discipline a local clock signal to the master clock frequency responsively to the received clock signal; and

output the disciplined local clock signal via the clock output port to the second compute node.

15. The system according to claim 1 , wherein the compute nodes are configured to distribute the master clock frequency via respective ones of the clock connections using at least one of: a one pulse per second (PPS) signal; or a 10 mega Hertz (10 MHz) signal.

16. A synchronized communication method, comprising:

connecting compute nodes including a first compute node, one or more intermediate compute nodes, and a last compute node, with clock connections in a closed loop configuration so that each of the compute nodes has an output connected to an input of a next one of the compute nodes via a respective one of the clock connections, while the last compute node has an output connected to an input of the first compute node via another respective one of the clock connections;

distributing among the compute nodes, via ones of the clock connections, a master clock frequency from any selected one of the compute nodes, which is designated as a master clock;

at a first time, designating one of the plurality of compute nodes as the master clock and distributing the master clock frequency among the compute nodes; and

at a second time, designating another one of the plurality of compute nodes as the master clock, and distributing the master clock frequency among the compute nodes.

17. The method according to claim 16 , further comprising selectively blocking and unblocking distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.

18. The method according to claim 16 , wherein the compute nodes include at least one of the following: a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.

19. The method according to claim 16 , further comprising:

recovering a remote clock;

connecting a clock input port to a clock output port of a third compute node of the plurality of compute nodes via a first one of the clock connections;

receiving a clock signal at the master clock frequency from the third compute node; and

connecting a clock output port to a clock input port of a second compute node of the plurality of compute nodes via a second one of the clock connections.

20. The method according to claim 19 , wherein the third compute node and the second compute node are a same one of the compute nodes.

21. The method according to claim 19 , further comprising:

disciplining a local clock signal to the master clock frequency responsively to: the recovered respective remote clock; or the received clock signal; and

outputting the disciplined local clock signal via the clock output port to the second compute node.

22. The method according to claim 19 , further comprising:

disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock; and

outputting the disciplined local clock signal via the clock output port to the second compute node.

23. The method according to claim 22 , further comprising ignoring the clock signal received by the clock input port.

24. The method according to claim 23 , further comprising selectively blocking distribution of the master clock frequency in the closed loop by instructing clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.

25. The method according to claim 19 , further comprising:

disciplining a local clock signal to the master clock frequency responsively to the received clock signal; and

outputting the disciplined local clock signal via the clock output port to the second compute node.

26. The method according to claim 16 , further comprising distributing the master clock frequency via respective ones of the clock connections using at least one of: a one pulse per second (PPS) signal; or a 10 mega Hertz (10 MHz) signal.