Metadata registers for a memory device
This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.
1 . A DRAM memory, comprising:
a DRAM cell memory array comprising a first portion and a second portion;
a memory I/O module coupled to the DRAM cell memory array having a plurality of metadata registers, wherein at least one second register of the plurality of metadata registers is configured to associate to a column location of the second portion of the DRAM cell memory array;
the memory I/O module further configured to perform operations comprising:
receiving data from a host;
receiving metadata from the host into the at least one second register of the plurality of metadata registers;
storing the data in the first portion of the DRAM cell memory array; and
storing the metadata in the column location of the second portion of the DRAM cell memory array.
2 . The DRAM memory of claim 1 , wherein the data and the metadata are received simultaneously during a single write command.
3 . The DRAM memory of claim 1 , wherein the memory I/O module is further configured for performing operations comprising:
receiving a first address through at least one non-data connection corresponding to the data,
wherein:
storing the data in the first portion of the DRAM cell memory array is based on the first address; and
storing the metadata in the column location of the second portion of the DRAM cell memory array is to a second address corresponding to the first address.
4 . The DRAM memory of claim 1 , wherein:
receiving metadata from the host into the at least one second register comprises receiving a plurality of metadata comprising first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of a page of the DRAM cell memory array; and
storing the metadata in the column location of the second portion of the DRAM cell memory array comprises writing the plurality of metadata into the page of the DRAM cell memory array from the at least one second register to complete the first write operation and the second write operation.
5 . The DRAM memory of claim 1 , wherein the metadata comprises an error correction code (ECC).
6 . The DRAM memory of claim 1 , wherein the metadata comprises a signature for authenticating the data corresponding to the metadata.
7 . The DRAM memory of claim 1 , wherein the memory I/O module further comprises a data mask inversion (DMI) portion, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of at least one data connection.
8 . The DRAM memory of claim 1 , wherein the memory I/O module further comprises a read data strobe (RDQS) portion, wherein a number of connections of the read data strobe (RDQS) portion is less than a number of connections of at least one data connection.
9 . The DRAM memory of claim 1 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on a memory address for the data associated with the metadata specified by a write command received by the memory I/O module corresponding to the data.
10 . The DRAM memory of claim 1 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on an indicator specified by a write command received by the memory I/O module.
11 . A method, comprising:
receiving data, at a DRAM memory device, into at least one first register;
receiving metadata, at the DRAM memory device, into at least one second register of a plurality of metadata registers;
storing, by the DRAM memory device, the data from the at least one first register into a first portion of a DRAM cell memory array; and
storing, by the DRAM memory device, the metadata from the at least one second register into a column location of a second portion of the DRAM cell memory array, wherein the at least one second register of the plurality of metadata registers is configured to associate to the column location of the second portion of the DRAM cell memory array.
12 . The method of claim 11 , further comprising:
retrieving the data from the DRAM cell memory array into the at least one first register;
retrieving the metadata from the DRAM cell memory array into the at least one second register;
transmitting the data to a host from the at least one first register; and
transmitting the metadata to the host from the at least one second register.
13 . The method of claim 11 , further comprising:
receiving a first address through at least one non-data connection corresponding to the data,
wherein:
storing the data in the first portion of the DRAM cell memory array is based on the first address; and
storing the metadata in the second portion of the DRAM cell memory array is to a second address corresponding to the first address.
14 . The method of claim 11 , wherein:
receiving metadata from a host into the at least one second register comprises receiving a plurality of metadata comprising first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of a page of the DRAM cell memory array; and
storing the metadata in the second portion of the DRAM cell memory array comprises writing the plurality of metadata into the page of the DRAM cell memory array from the at least one second register to complete the first write operation and the second write operation.
15 . The method of claim 11 , wherein the metadata comprises an error correction code (ECC).
16 . The method of claim 11 , wherein the metadata comprises a signature for authenticating the data corresponding to the metadata.
17 . The method of claim 11 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on a memory address for the data associated with the metadata specified by a write command corresponding to the data.
18 . The method of claim 11 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on an indicator specified by a write command.
19 . A method, comprising:
retrieving data from a first portion of a DRAM cell memory array into at least one first register;
retrieving metadata from a column location of a second portion of the DRAM cell memory array into at least one second register of a plurality of metadata registers, wherein at least one second register of the plurality of metadata registers is configured to associate to the column location of the second portion of the DRAM cell memory array;
transmitting the data to a host from the at least one first register; and
transmitting the metadata to the host from the at least one second register.
20 . The method of claim 19 , wherein the data and the metadata are retrieved simultaneously during a single read command.
21 . The method of claim 19 , further comprising:
receiving a first address through at least one second non-data connection corresponding to the data,
wherein:
retrieving the data from the first portion of the DRAM cell memory array is based on the first address; and
retrieving the metadata from the second portion of the DRAM cell memory array is from a second address corresponding to the first address.
22 . The method of claim 19 , wherein:
retrieving metadata from the second portion of the DRAM cell memory array into the at least one second register comprises retrieving a plurality of metadata comprising first metadata corresponding to a first read operation and second metadata corresponding to a second read operation during a single page operation, the plurality of metadata corresponding to a plurality of memory addresses of a page of the DRAM cell memory array; and
transmitting metadata to the host from the at least one second register comprises transmitting the plurality of metadata.
23 . The method of claim 19 , wherein the metadata comprises an error correction code (ECC).
24 . The method of claim 19 , wherein the metadata comprises a signature for authenticating the data corresponding to the metadata.
25 . The method of claim 19 , wherein retrieving the metadata comprises retrieving the metadata based on a memory address for the data associated with the metadata specified by a read command corresponding to the data.
26 . The method of claim 19 , wherein retrieving the metadata comprises retrieving the metadata based on an indicator specified by a read command.
27 . A DRAM memory, comprising:
a host device configured to communicate with a DRAM memory device through a channel,
the host device comprising a memory controller coupled to the channel, the memory controller configured perform operations including:
transmitting data between the memory controller and at least one first register of the DRAM memory device; and
transmitting metadata between the memory controller and at least one second register of a plurality of metadata registers of the DRAM memory device, wherein the at least one second register of the plurality of metadata registers including a first portion associated with a first column address of a DRAM cell memory array and a second portion associated with a second column address of the DRAM cell memory array.
28 . The DRAM memory of claim 27 , wherein the operations comprise signaling a read command on the channel specifying at least one read address for retrieving the data and retrieving the metadata from the DRAM memory device.
29 . The DRAM memory of claim 28 , wherein the at least one read address identifies a set of the at least one second register for storing the metadata.
30 . The DRAM memory of claim 28 , wherein the read command comprises an indicator specifying a set of the at least one second register for storing the metadata.
31 . The DRAM memory of claim 27 , wherein the operations comprise signaling a write command on the channel specifying a write address for storing the data and transmitting the data to the DRAM memory device.
32 . The DRAM memory of claim 31 , wherein the write address identifies a set of the at least one second register for storing the metadata.
33 . The DRAM memory of claim 31 , wherein the write command comprises an indicator specifying one of the at least one second register for storing the metadata.