Bit error management in memory devices
In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
1 . A method, comprising:
receiving, by a memory device, a command to read data in a first format from a memory, the data being stored in a second format in the memory, the second format comprising a plurality of copies of the data in the first format;
comparing, by the memory device and using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data;
storing, by the memory device, the dominant bit state for bits of the data in the memory as error-corrected data in the first format; and
causing, by the memory device, the error-corrected data to be read from the memory in the first format as a response to the command to read the data in the first format.
2 . The method of claim 1 , wherein the memory is a first memory, the method further comprising:
receiving another command to program a single copy of the data in the first format in the first memory;
storing the single copy of the data to a second memory based on receiving the other command to program the data;
causing the plurality of copies of the data to be copied from the single copy of the data in the second memory to a data cache of the first memory, the plurality of copies comprising the second format of the data; and
programming the plurality of copies of the data in the second format from the data cache to an array in the first memory.
3 . A memory device, comprising:
a first memory;
a second memory; and
a controller configured to:
receive a command to read data in a first format from the first memory, the data being stored in a second format in the first memory, the second format comprising a plurality of copies of the data in the first format;
provide the plurality of copies of the data from the first memory to an error correction circuit;
compare, using the error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data;
store the dominant bit state for the bits of the data in the second memory as corrected data in the first format;
provide the corrected data from the second memory to the first memory; and
cause the corrected data to be read from the first memory in the first format as a response to the command to read the data in the first format.
4 . The memory device of claim 3 , wherein the command to read the data is an Open NAND Flash Interface (ONFI) read command.
5 . The memory device of claim 3 , wherein the error correction circuit comprises a plurality of adder circuits.
6 . The memory device of claim 5 , wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
identify a multi-bit output of the plurality of adder circuits; and
determine the dominant bit state based on a subset of bits of the multi-bit output.
7 . The memory device of claim 6 , wherein the subset of bits comprises a set of most significant bits (MSBs), and
wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
compare a first MSB, of the set of MSBs, with a second MSB, of the set of MSBs, to determine the dominant bit state.
8 . The memory device of claim 3 , wherein the error correction circuit comprises at least one inverter.
9 . The memory device of claim 8 , wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
identify a multi-bit output of the error correction circuit with the at least one inverter;
determine an erase error in the plurality of copies of the data based on the multi-bit output of the error correction circuit with the at least one inverter; and
output information identifying the erase error.
10 . The memory device of claim 3 , wherein the error correction circuit is configured to:
read the plurality of copies of the data from a single NAND column across multiple pages.
11 . The memory device of claim 3 , wherein the error correction circuit is disposed in a page buffer associated with the first memory or associated with a data path associated with the first memory.
12 . A memory device, comprising:
a first memory;
a second memory; and
a controller configured to:
write data in a first format to a data cache of the first memory;
provide the data from the data cache of the first memory to the second memory;
provide a plurality of copies of the data in the second memory to the data cache of the first memory, the plurality of copies comprising a second format of the data; and
program the plurality of copies of the data in the second format from the data cache of the first memory to a single array of the first memory.
13 . The memory device of claim 12 , wherein the controller is further configured to:
receive a command to program the data in the first format in the first memory, wherein writing the data in the first format to the data cache of the first memory is based on receiving the command.
14 . The memory device of claim 13 , wherein the command to program the data identifies a first range of addresses, and
wherein the plurality of copies of the data is programmed in a second range of addresses that includes the first range of addresses.
15 . The memory device of claim 14 , wherein the first range of addresses represents a portion of a single page of the first memory, and
wherein the second range of addresses represents an entirety of the single page of the first memory.
16 . The memory device of claim 13 , wherein the command to program the data is an Open NAND Flash Interface (ONFI) write command.
17 . The memory device of claim 12 , wherein the first memory comprises a non-volatile memory, and
wherein the second memory comprises a volatile memory.
18 . The memory device of claim 12 , wherein a first copy of the data and a second copy of the data are mirrored across a plurality of pages of the first memory.
19 . The memory device of claim 12 , wherein a first copy of the data and a second copy of the data are mirrored across one of:
a common write-line across different blocks,
different write-lines across a common block, or
different write-lines across different blocks.
20 . The memory device of claim 12 , wherein the data is associated with a security operation for chip initialization of the memory device.