Bit error management in memory devices
In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
1. A memory device, comprising:
a volatile memory;
a non-volatile memory; and
a controller configured to:
receive a command to read data in a first format from the non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format;
provide the plurality of copies of the data from the non-volatile memory to an error correction circuit;
compare, using the error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data;
store the dominant bit state for the bits of the data in the volatile memory as corrected data in the first format;
provide the corrected data from the volatile memory to the non-volatile memory; and
cause the corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
2. The memory device of claim 1 , wherein the command to read the data is an Open NAND Flash Interface (ONFI) read command.
3. The memory device of claim 1 , wherein the error correction circuit comprises a plurality of adder circuits.
4. The memory device of claim 3 , wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
identify a multi-bit output of the plurality of adder circuits; and
determine the dominant bit state based on a subset of bits of the multi-bit output.
5. The memory device of claim 4 , wherein the subset of bits comprises a set of most significant bits (MSBs), and
wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
compare a first MSB, of the set of MSBs, with a second MSB, of the set of MSBs, to determine the dominant bit state.
6. The memory device of claim 1 , wherein the error correction circuit comprises at least one inverter.
7. The memory device of claim 6 , wherein the controller, when configured to compare the plurality of copies of the data to determine the dominant bit state, is configured to:
identify a multi-bit output of the error correction circuit with the inverter;
determine an erase error in the plurality of copies of the data based on the multi-bit output of the error correction circuit with the at least one inverter; and
output information identifying the erase error.
8. The memory device of claim 1 , wherein the error correction circuit is configured to:
read the plurality of copies of the data from a single NAND column across multiple pages.
9. The memory device of claim 1 , wherein the error correction circuit is disposed in a page buffer associated with the non-volatile memory or associated with a data path associated with the non-volatile memory.
10. A memory device, comprising:
a volatile memory;
a non-volatile memory; and
a controller configured to:
receive a command to program data in a first format in the non-volatile memory;
write the data to a secondary data cache of the non-volatile memory based on receiving the command to program the data in the non-volatile memory;
provide the data from the secondary data cache of the non-volatile memory to the volatile memory;
provide a plurality of copies of the data in the volatile memory to the secondary data cache of the non-volatile memory, the plurality of copies comprising a second format of the data; and
program the plurality of copies of the data in the second format from the secondary data cache of the non-volatile memory to a single array of the non-volatile memory.
11. The memory device of claim 10 , wherein the command to program the data identifies a first range of addresses, and
wherein the plurality of copies of the data is programmed in a second range of addresses that includes the first range of addresses.
12. The memory device of claim 11 , wherein the first range of addresses represents a portion of a single page of the volatile memory, and
wherein the second range of addresses represents an entirety of the single page of the non-volatile memory.
13. The memory device of claim 10 , wherein a first copy of the data and a second copy of the data are mirrored across a plurality of pages of the non-volatile memory.
14. The memory device of claim 10 , wherein the command to program the data is an Open NAND Flash Interface (ONFI) write command.
15. The memory device of claim 10 , wherein a first copy of the data and a second copy of the data are mirrored across one of:
a common write-line across different blocks,
different write-lines across a common block, or
different write-lines across different blocks.
16. The memory device of claim 10 , wherein the data is associated with a security operation for chip initialization of the memory device.
17. The memory device of claim 10 , wherein a quantity of copies of the data is 8 copies of the data or 16 copies of the data.
18. The memory device of claim 10 , wherein a quantity of copies of the data is greater than 3 copies of the data.
19. A method, comprising:
receiving, by a memory device, a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format;
comparing, by the memory device and using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data;
storing, by the memory device, the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format; and
causing, by the memory device, the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
20. The method of claim 19 , further comprising:
receiving another command to program a single copy of the data in the first format in the non-volatile memory;
storing the single copy of the data to volatile memory based on receiving the other command to program the data;
causing the plurality of copies of the data to be copied from the single copy of the data in the volatile memory to a data cache of the non-volatile memory, the plurality of copies comprising the second format of the data; and
programming the plurality of copies of the data in the second format from the data cache to an array in the non-volatile memory.
21. The method of claim 19 , further comprising:
inverting a first subset of the plurality of copies of the data such that the first subset has opposite bit values relative to a second subset of the plurality of copies of the data; and
wherein comparing the plurality of copies of the data comprises:
comparing the plurality of copies of the data based on inverting the first subset of the plurality of copies of the data.
22. The method of claim 19 , wherein receiving the command to read the data comprises:
receiving the command to receive the data before system firmware of a system, which includes the memory device, is loaded.
23. The method of claim 19 , wherein the first format is associated with a first range of addresses in an array of the non-volatile memory and the second format is associated with a second range of addresses in the array of the non-volatile memory.
24. The method of claim 23 , wherein the second range of addresses includes the first range of addresses.
25. The method of claim 23 , wherein the first range of addresses is a portion of a page of the array and the second range of addresses is an entirety of the page of the array.