Vertical power transistor device
A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.
1. A transistor device comprising a gate, a source, and a drain, wherein the gate and the source are separated from the drain by at least a JFET region, a spreading layer including a graded doping profile, and a drift layer, wherein a doping concentration of the spreading layer varies more than a factor of about 10 2 cm −3 between the JFET region and the drift layer.
2. The transistor device of claim 1 wherein the JFET region, the spreading layer, and the drift layer comprise silicon carbide.
3. The transistor device of claim 1 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
4. The transistor device of claim 1 wherein the JFET region has a first doping concentration, the spreading layer has a second doping concentration that is different from the first doping concentration, and the drift layer has a third doping concentration that is different from the first doping concentration and the second doping concentration.
5. The transistor device of claim 4 wherein the spreading layer has a doping concentration in the range of approximately 2×10 17 cm −3 to approximately 5×10 16 cm −3 .
6. The transistor device of claim 4 wherein the JFET region has a doping concentration in the range of approximately 1×10 16 cm −3 to approximately 2×10 17 cm −3 .
7. The transistor device of claim 1 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1 micron.
8. The transistor device of claim 1 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
9. The transistor device of claim 1 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
10. The transistor device of claim 1 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm 2 .
11. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm 2 .
12. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm 2 .
13. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer having a graded doping profile such that a doping concentration of the spreading layer varies more than a factor of about 10 2 cm −3 between a JFET region and the drift layer;
a pair of junction implants in the spreading layer and separated by the JFET region, each one of the pair of junction implants comprising a deep well region, a base region, and a source region;
a gate contact and a source contact on the spreading layer, such that the gate contact partially overlaps and runs between each source region in the pair of junction implants; and
a drain contact on the substrate opposite the drift layer.
14. The transistor device of claim 13 further comprising a gate oxide layer between the gate contact and the spreading layer.
15. The transistor device of claim 13 wherein the source contact is divided into two sections, and each section of the source contact is on a portion of the spreading layer such that each section of the source contact partially overlaps both the source region and the deep well region of each one of the pair of junction implants, respectively.
16. The transistor device of claim 13 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
17. The transistor device of claim 13 wherein the drift layer and the spreading layer comprise silicon carbide.
18. The transistor device of claim 13 wherein a width of the JFET region is approximately 3 microns or less.
19. The transistor device of claim 18 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm 2 .
20. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm 2 .
21. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm 2 .
22. The transistor device of claim 13 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
23. The transistor device of claim 13 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
24. The transistor device of claim 13 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1.0 microns.
25. The transistor device of claim 13 wherein a thickness of each one of the pair of junction implants is in the range of approximately 1.0 microns to approximately 2.0 microns.
26. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a JFET region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is in a range from 1.0 to 2.5 microns and is provided at a fourth depth that is greater than the first depth, and
wherein a thickness of the JFET region is in a range from 0.75 to 1.5 microns.
27. The transistor device of claim 26, wherein the transistor device comprises silicon carbide.
28. The transistor device of claim 26, further comprising a gate contact, a drain contact, and a source contact.
29. The transistor device of claim 28, wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
30. The transistor device of claim 28, further comprising a channel regrowth layer between the gate contact and the JFET region, the channel regrowth layer comprising the first doping type with a doping concentration that is less than a doping concentration of the JFET region.
31. The transistor device of claim 30, wherein the doping concentration of the channel regrowth layer is less than a doping concentration of the spreading layer at an interface between the spreading layer and the drift layer.
32. The transistor device of claim 31, wherein the spreading layer has a doping concentration in a range from 2×10 17 cm −3 to 5×10 16 cm −3 and the channel regrowth layer has the doping concentration in a range from 1×10 15 cm −3 to 1×10 17 cm −3 .
33. The transistor device of claim 26, wherein a channel width of the transistor device is less than 3 microns.
34. The transistor device of claim 33, wherein an on-state resistance of the transistor device is between 1.8 mΩ/cm 2 and 2.2 mΩ/cm 2 , and a blocking voltage of the transistor device is rated to handle between 600 volts and 1200 volts.
35. The transistor device of claim 26, wherein a thickness of each of the junction implants in the pair of junction implants is in a range from 1.0 to 2.0 microns.
36. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a JFET region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein a width of the spreading layer at the second depth and between the base region of each of the junction implants in the pair of junction implants is less than a width of the spreading layer at the first depth and between the well region of each of the junction implants in the pair of junction implants.
37. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a JFET region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein the doping concentration of the spreading layer at the third depth is greater than or equal to a doping concentration of the JFET region.
38. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a JFET region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein the base region of each of the junction implants in the pair of junction implants is positioned between the respective well region of the respective junction implants in the pair of junction implants and the JFET region.