IP Library Granted Patent US 6,838,770
Granted Patent B2
US 6,838,770 · App. 09/891,356 · Granted Jan 4, 2005

Semiconductor device, designing method and designing device thereof

Assignee: Mitsubishi Denki Kabushiki Kaisha
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Quick Facts
Patent No.
US 6,838,770
App. No.
09/891,356
Granted
Jan 4, 2005
Kind
B2
Abstract

A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.

Claims (17)

1. A semiconductor device comprising:

a plurality of wiring layers vertically overlapping with each other, including a first layer and a second layer; a power-supply wire; and a ground wire;

wherein said first layer and said second layer include a dummy pattern, each arranged to alleviate for a difference in density in a planar layout of wiring pattern in a same layer,

said dummy pattern of said first layer and said dummy pattern of said second layer are electrically connected with each other and further electrically connected to a reference wire which is either said power-supply wire or said ground wire.

2. The semiconductor device according to claim 1 , wherein electrical connection between said dummy pattern and said reference wire is made through paths formed by a process including a first step of:

setting all said dummy patterns as unconnected dummy patterns, and a second step of:

retrieving any said unconnected dummy patterns that overlap each other and are adjacent to each other in an up and down direction with not less than a predetermined distance using a target wire which is either said reference wire or wires having the same electrical potential as said reference wire as the starting point,

in the case when, as a result of said retrieval, any of such said unconnected dummy patterns are detected, recognizing these as adjacent dummy patterns and providing an interlayer connection between said target wire and said adjacent dummy patterns, as well as changing the setting of said adjacent dummy patterns as non-unconnected dummy patterns with said adjacent dummy patterns being set as those having the same electric potential as said target wire,

recursively repeating said second step with respect to all said reference wires and those wires having the same electrical potential as said reference wire,

in place of said reference wire, with the other of said power-supply wire and said ground wire being newly used as a reference wire, recursively repeating said second step with respect to all said reference wires and those wires having the same electrical potential as said reference wire.

3. A designing device of a semiconductor device comprising:

a dummy pattern generation means for generating dummy patterns so as to eliminate a difference in density in a wiring pattern based upon wiring layout information that has been provided;

an unconnected dummy pattern setting means for setting all said dummy patterns as unconnected dummy patterns so as to electrically connect said dummy patterns and said reference wire with one of a power-supply wire and a ground wire being used as a reference wire based upon layout information of a power-supply wire and a ground wire that has been supplied;

a first recursive process executing means which retrieves any said unconnected dummy patterns that overlap each other and are adjacent to each other in an up and down direction with not less than a predetermined distance using a target wire which is either said reference wire or wires having the same electrical potential as said reference wire as the starting point for a dummy pattern connection process,

which in said case when, as a result of said retrieval, any of such unconnected dummy patterns are detected, recognizes these as adjacent dummy patterns and provides an interlayer connection between said target wire and said adjacent dummy patterns, as well as changing the setting of said adjacent dummy patterns as non-unconnected dummy patterns with said adjacent dummy patterns being set as those having said same electric potential as said target wire,

which recursively repeats said sequence of jobs with respect to all said reference wire and those wires having the same electrical potential as said reference wire, and

a second recursive process job executing means which, in place of said reference wire, with the other of said power-supply wire and said ground wire being newly used as said reference wire, recursively repeats said dummy pattern connection process with respect to all said reference wires and those wires having said same electrical potential as said reference wire.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2011
From: MITSUBISHI DENKI KABUSHIKI KAISHA
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025980/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2001
From: ITOH, NIICHI
To: MITSUBISHI DENKI KABUSHIKI KAISHA
Reel/Frame 011953/0923 →
Priority Claims (1)
JP 2000-251861 · Aug 23, 2000 · national
Continuity (1)
Related Publication 20020024148A1 · Feb 28, 2002