Gate technology for strained surface channel and strained buried channel MOSFET devices
A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si 1−x Ge x layer on a substrate, a strained channel layer on the relaxed Si 1−x Ge x layer, and a Si 1−y Ge y layer; removing the Si 1−y Ge y layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
1. A method of fabricating a semiconductor device, the method comprising the steps of:
(a) providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer;
(b) providing at least one sacrificial layer disposed above the strained layer;
(c) removing at least a portion of the at least one sacrificial layer, wherein the strained layer remains intact after removal; and
(d) providing a gate dielectric above the strained layer.
2. The method of claim 1 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate, and a strained layer consisting of at least one of Si, Ge, and SiGe, the strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
3. The method of claim 1 wherein step (b) comprises:
providing at least one sacrificial layer comprising Si, the at least one sacrificial layer being disposed above the strained layer.
4. The method of claim 1 wherein step (b) comprises:
providing at least one sacrificial layer comprising SiGe, the at least one sacrificial layer being disposed above the strained layer.
5. The method of claim 1 wherein step (b) comprises:
providing multiple sacrificial layers disposed above the strained layer, wherein some of the multiple sacrificial layers comprise Si and other multiple sacrificial layers comprise SiGe.
6. The method of claim 1 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate comprising Si, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
7. The method of claim 1 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a layer of SiO 2 disposed on a Si substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
8. The method of claim 1 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a graded buffer layer disposed on a Si substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
9. The method of claim 1 wherein step (c) comprises:
removing at least a portion of the at least one sacrificial layer using a wet oxidation technique, wherein the strained layer remains intact after oxidation.
10. The method of claim 9 wherein the wet oxidation technique is utilized at a temperature up to about 750° C.
11. The method of claim 1 wherein step (c) comprises:
removing at least a portion of the at least one sacrificial layer using a dry oxidation technique, wherein the strained layer remains intact after oxidation.
12. The method of claim 1 wherein step (d) comprises:
providing a gate dielectric above the strained layer, wherein at least a portion of the strained layer is oxidized to provide the gate dielectric.
13. The method of claim 1 wherein step (d) comprises:
providing a gate dielectric above the strained layer, wherein a dielectric layer is deposited above the strained layer to provide the gate dielectric.
14. The method of claim 1 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer, the strained layer being substantially free of misfit dislocations.
15. A method of fabricating a semiconductor device, the method comprising the steps of:
(a) providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer;
(b) providing at least one sacrificial layer disposed above the strained layer;
(c) removing at least a portion of the at least one sacrificial layer, wherein a small amount of the strained layer is removed during removal; and
(d) providing a gate dielectric above the strained layer.
16. The method of claim 15 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on substrate, and a strained layer consisting of at least one of Si and Ge having a thickness of less than 300 angstroms disposed on the relaxed layer.
17. The method of claim 15 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a substrate comprising Si, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
18. The method of claim 15 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a layer of SiO 2 disposed on a Si substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
19. The method of claim 15 wherein step (a) comprises:
providing a semiconductor heterostructure, the heterostructure including a relaxed Si 1−x Ge x layer disposed on a graded buffer layer disposed on a Si substrate, and a strained layer having a thickness of less than 300 angstroms disposed on the relaxed layer.
20. The method of claim 15 wherein step (c) comprises:
removing at least a portion of the at least one sacrificial layer using a wet oxidation technique, wherein a small amount of the strained layer is removed during oxidation.
21. The method of claim 20 wherein the wet oxidation technique is utilized at a temperature up to about 750° C.
22. The method of claim 15 wherein step (c) comprises:
removing at least a portion of the at least one sacrificial layer using a dry oxidation technique, wherein a small amount of the strained layer is removed during oxidation.
23. The method of claim 15 wherein step (c) comprises:
removing at least a portion of the at least one sacrificial layer, wherein less than 10 angstroms of the strained layer is removed.
24. The method of claim 15 wherein step (d) comprises:
providing a gate dielectric above the strained layer, wherein at least a portion of the strained layer is oxidized to provide the gate dielectric.
25. The method of claim 15 wherein step (d) comprises:
providing a gate dielectric above the strained layer, wherein a dielectric layer is deposited above the strained layer to provide the gate dielectric.
26. The method of claim 15 wherein step (a) comprises:
providing a semiconductor heterostructure, the structure including a relaxed Si 1−x Ge x layer disposed on a substrate, and a strained layer having a thickness less than 300 angstroms disposed on the relaxed layer, the strained layer being substantially free of misfit dislocations.