IP Library Granted Patent US 6,853,204
Granted Patent B2
US 6,853,204 · App. 10/208,818 · Granted Feb 8, 2005

Wafer inspection method of charging wafer with a charged particle beam then measuring electric properties thereof, and inspection device based thereon

Assignee: Hitachi, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,853,204
App. No.
10/208,818
Granted
Feb 8, 2005
Kind
B2
Abstract

A semiconductor defect inspection device and method for detecting defects of partially finished substrates (semiconductor wafers) for semiconductor devices is provided. The substrate surface is irradiated with a charged particle beam and a voltage contrast image is obtained while the charged voltage is controlled at a desired level, and the electric resistances of the irradiated area from the image are calculated to detect a defect and identify the type of defect. Further, the distribution of electric resistances on the whole surface of the substrate can be quickly worked out. The charged particle beam irradiation conditions are varied in order to bring the charged voltage of the area to a desired value. With this device/method, electric resistances of small portions at desired charged voltages and the corresponding electric resistances are measured in a non-contact manner to determine the type of defect. When this inspection method is applied to the PCB manufacturing process, defects can be detected and remedied at an early stage of the process. Consequently, in the semiconductor devices and other PCB related devices, the defect rate decreases and the productivity increase. Since the defect occurrence rate is reduced, the reliability of semiconductor devices is increased, and the efficiency in developing new products is improved.

Claims (17)

1. A semiconductor defect inspection device, comprising:

deciding means for deciding irradiation conditions of a charged particle beam which include an electric current value of the charged particle beam;

scanning means for scanning a specific area on a to-be-inspected object with the charged particle beam;

measuring means for measuring an electron count and an energy level of at least one of secondary electrons and back scattering electrons emitted from the specific area;

calculation means for calculating a charged voltage of the specific area based upon the energy level, and for calculating a corresponding electric resistance value based upon the electron count and the electric current value of the charged particle beam; and

comparing means for comparing a charged voltage vs. electric resistance characteristic pattern of the to-be-tested object being composed of the changed voltage and the corresponding electric resistance value with the charged voltage vs. electric resistance characteristic pattern of said type of defect to determine whether said type of defect exists in the specific area.

2. The semiconductor defect inspection device according to claim 1 , further comprising:

an image processing section for making a voltage contrast image based upon scanned results from the scanning means by scanning a plurality of areas on the to-be-tested object with the charged particle beam and measured results from the measuring means by measuring an electron count and an energy level of at least one of secondary electrons and back scattering electrons emitted from each of the plurality of areas; and

preliminary defect determining means for comparing a brightness of each area in the voltage contrast image thereby preliminarily determining at least one specific area containing at least one defect.

3. The semiconductor defect inspection device according to claim 2 , further comprising calibrating means for calibrating a signal scale of the voltage contrast image with the charged voltage vs. electric resistance characteristic pattern of at least one type of defect.

4. The semiconductor defect inspection device according to claim 1 , further comprising:

a holder for holding a to-be-inspected object; and

a detector for detecting at least one of secondary electrons and back scattering electrons emitted from the specific area,

wherein the scanning means includes an objective lens.

5. The semiconductor defect inspection device according to claim 4 , further comprising at least one of a position calibration pattern on the holder, an optical image, and a voltage contrast image, for aligning the holder with the scanning means.

6. The semiconductor defect inspection device according to claim 1 , wherein the measuring section includes an electrode for varying the charged voltage by applying a voltage to the surface of the object.

7. The semiconductor defect inspection device according to claim 1 , wherein the object is a wafer bearing at least one semiconductor device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2002
From: NISHIYAMA, HIDETOSHI; NOZOE, MARI
To: HITACHI, LTD.
Reel/Frame 013278/0034 →
Priority Claims (1)
JP 2001-295399 · Sep 27, 2001 · national
Continuity (1)
Related Publication 20030057971A1 · Mar 27, 2003