Junction-isolated depletion mode ferroelectric memory devices
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
1. A ferroelectric memory cell, comprising:
a control gate formed overlying a ferroelectric layer;
a first source/drain region having a first conductivity type;
a second source/drain region having the first conductivity type;
a channel region interposed between the first and second source/drain regions and having the first conductivity type; and
a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate.
2. The ferroelectric memory cell of claim 1 , further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; and
a floating gate interposed between the gate dielectric layer and the ferroelectric layer.
3. The ferroelectric memory cell of claim 2 , wherein the floating gate comprises a conductive material.
4. The ferroelectric memory cell of claim 3 , wherein the conductive material includes at least one material selected from the group consisting of conductively-doped polysilicon, metal silicides, metals and metal alloys.
5. The ferroelectric memory cell of claim 4 , wherein the floating gate comprises a metal layer overlying a conductively-doped polysilicon layer.
6. The ferroelectric memory cell of claim 1 , wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
7. The ferroelectric memory cell of claim 1 , further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer;
wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
8. The ferroelectric memory cell of claim 1 , wherein the ferroelectric layer is overlying and adjoining the channel region.
9. A ferroelectric memory cell, comprising:
a control gate formed overlying a ferroelectric layer;
a first source/drain region having a first conductivity type;
a second source/drain region having the first conductivity type;
a channel region interposed between the first and second source/drain regions and having the first conductivity type; and
a well having a second conductivity type formed in the second source/drain region, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate.
10. The ferroelectric memory cell of claim 9 , further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; and
a conductive floating gate interposed between the gate dielectric layer and the ferroelectric layer.
11. The ferroelectric memory cell of claim 9 , wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
12. The ferroelectric memory cell of claim 9 , further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer;
wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
13. The ferroelectric memory cell of claim 9 , wherein the ferroelectric layer is overlying and adjoining the channel region.
14. The ferroelectric memory cell of claim 9 , wherein the ferroelectric memory cell is formed on a silicon-on-insulator substrate.
15. The ferroelectric memory cell of claim 9 , wherein the well is interposed between the second source/drain region and a bit line coupled to the memory cell.
16. A memory cell, comprising:
a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first source/drain region having the first conductivity type formed in the first well region and coupled to a program line;
a second source/drain region having the first conductivity type formed in the first well region;
a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions; and
a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate.
17. A memory cell, comprising:
a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first source/drain region having the first conductivity type formed in the first well region and coupled to a program line;
a second source/drain region having the first conductivity type formed in the first well region;
a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions; and
a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate.