Multichip module, manufacturing method thereof, multichip unit and manufacturing method thereof
Reduction of parasitic capacitance originated between semiconductor chip and optical chip by reducing the connection distance thereof by means of interlayer-connecting the semiconductor chip mounted on a surface of a resin layer and the optical chip buried on another surface of the resin layer with an interlayer via.
1. A multichip module comprising:
a circuit section having an insulating layer, a patterned interconnect having connection lands formed on first and second surfaces of said insulating layer and an interlayer via for electrically interlayer connect said connection lands formed said first and second surfaces of said insulating layer;
an electric chip having connection terminals connected to said connection lands, and mounted on said first surface of said insulating layer with said connection terminals connected to said connection lands for processing an electric signal inputted and/or outputted through said interlayer via; and
an optical chip having a terminal section connected through said interlayer via to said connection land with said connection terminal connected thereto, having a light emitting section and/or a photo detecting section formed on a surface thereof and buried in said insulating layer with said surface coinciding with a second surface of said insulating layer so that said light emitting section and/or said photo detecting section is exposed on said second surface of said insulating layer.
2. The multichip module according to claim 1 , wherein:
said circuit section comprises said patterned interconnect formed on a surface of a plurality of said insulating layers which are stacked and said interlayer via interlaying said patterned interconnect;
said electric chip is mounted on an uppermost layer among said stacked plurality of insulating layers; and
said optical chip is buried in a lowermost layer among said stacked plurality of insulating layers.
3. The multichip module according to claim 1 , wherein said optical chip is buried in a direction of thickness of said insulating layer and within a region of projection of said electric chip.
4. A multichip unit comprising:
a multichip module comprising:
a circuit section having an insulating layer, a patterned interconnect having connection lands formed on first and second surfaces of said insulating layer and an interlayer via for electrically interlayer connect said connection lands formed said first and second surfaces of said insulating layer;
an electric chip having connection terminals connected to said connection lands, and mounted on the a surface of said insulating layer with said connection terminals connected to said connection lands for processing an electric signal inputted and/or outputted through said interlayer via; and
an optical chip having a terminal section connected through said interlayer via to said connection land with said connection terminal connected thereto, having a light emitting section and/or a photo detecting section formed on a surface thereof and buried in said insulating layer with said surface coinciding with a second surface of said insulating layer so that said light emitting section and/or said photo detecting section is exposed on said second surface of said insulating layer; and
anoptoelectrical interconnect layer comprising:
an optical transmission line formed on a second surface of said insulating layer of said multichip module, for optically connecting said light emitting section and said photo detecting section exposed on said second surface of said insulating layer; and
a via electrically connected with said connection land of said multichip module.
5. The multichip unit according to claim 4 , wherein said optical transmission line of saidoptoelectrical interconnect layer comprises an optical wave-guide for making an optical signal generated in said emitting section reflect and propagate to said photo detecting section.
6. The multichip unit according to claim 4 , wherein:
said circuit section of said multichip module comprises said patterned interconnect formed on a surface of a plurality of said insulating layers which are stacked, and said interlayer via interlaying said patterned interconnect;
said electric chip is mounted on an uppermost layer among said stacked plurality of insulating layers; and
said optical chip is buried in a lowermost layer among said stacked plurality of insulating layers.
7. The multichip unit according to claim 4 , wherein said optical chip is buried in a direction of thickness of said insulating layer and within a region of projection of said electric chip.