Trench DRAM cell with vertical device and buried word lines
A DRAM array having trench capacitor cells of potentially 4F 2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.
1. An integrated circuit memory cell comprising:
a substrate;
a trench capacitor formed in said substrate and having a conductive area and a capacitor dielectric between the conductive area and said substrate;
a vertically stacked transistor comprising first, second and third stacked conductivity regions over said substrate, the second stacked conductivity region being of a first conductivity type, and the first and third stacked conductivity regions being of a second conductivity type, wherein the second stacked conductivity region is between said first and third stacked conductivity regions, said vertically stacked transistor having a first vertical side and a second vertical side, wherein one of the first and second vertical sides of the vertically stacked transistor at said first stacked conductivity region is in contact with the conductive area of said trench capacitor;
a word line positioned to gate the second stacked conductivity region of said transistor; and
a bit line in contact with said third stacked conductivity region.
2. The memory cell of claim 1 , wherein the cell is a dynamic random access memory cell.
3. The memory cell of claim 1 , further comprising a body line positioned on the other vertical side of the second stacked conductivity region from the third insulating layer.
4. The memory cell of claim 3 , wherein the body line is a doped polysilicon line.
5. The memory cell of claim 4 , wherein the body line is doped to a first conductivity type.
6. The memory cell of claim 1 , wherein the first, second, and third conductive regions are doped polysilicon regions.
7. The memory cell of claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.
8. The memory cell of claim 1 , wherein the first conductivity type is n-type, and the second conductivity type is p-type.
9. The memory cell of claim 1 , wherein the capacitor dielectric layer is a layer of oxide.
10. The memory cell of claim 1 , wherein the capacitor dielectric layer is a layer of oxide-nitride.
11. The memory cell of claim 1 , wherein the capacitor dielectric layer is a layer of oxide-nitride.
12. The memory cell of claim 1 , wherein said trench capacitor is formed in a trench on one of the vertical sides of said vertically stacked transistor.
13. The memory cell of claim 12 , wherein the conductive area of said trench capacitor comprises a lower portion that extends across the entire width of the trench, and an upper portion that connects the lower portion to said vertically stacked transistor.
14. The memory cell of claim 12 , wherein the trench is on the same vertical side of said vertically stacked transistor as a body line.
15. The memory cell of claim 12 , wherein the trench is on a different vertical side of said vertically stacked transistor as a body line.
16. The memory cell of claim 1 , wherein the word line is a doped polysilicon line.
17. The memory cell of claim 16 , wherein the word line is doped to a second conductivity type.
18. The memory cell of claim 1 , wherein the bit line is a doped polysilicon line.
19. The memory cell of claim 18 , wherein the bit line is doped to a second conductivity type.
20. The memory cell of claim 1 , wherein the memory cell has an area of approximately 4F 2 or less, where F is the minimum lithographic feature size.
21. A memory device, comprising:
a substrate;
a trench capacitor over said substrate;
a vertical transistor over said substrate, said vertical transistor comprising a first active area electrically coupled at a vertical side thereof to said trench capacitor, a body region over said first active area, and a second active area over said body region;
an electrode spanning said body region configured to gate said first and second active areas;
a body line electrically coupled with said body region and configured to control the threshold voltage of said vertical transistor; and
a bit line electrically coupled to said second active area.