Embedded memory system and method including data error correction

1. In a graphics processing system having a memory system including an embedded memory array and having error-correction coding, a method for accessing the embedded memory array, comprising:

reading data and an associated error correction code from a location corresponding to a memory address in the embedded memory array;

storing the data at a buffer location in a buffer memory having a plurality of buffer locations for storing a plurality of data;

storing the memory address:

processing at least a portion of the data to provide modified data;

receiving write memory addresses; and

when writing the modified data to the embedded memory array in response to a write memory address matching the stored memory address,

logically combining the stored data and the modified data and storing the combined data at the buffer location;

calculating a new error correction code based on the combined data in the buffer memory; and

storing the combined data and the new error correction code to the location corresponding to the memory address in the embedded memory array.

2. The method of claim 1 wherein processing at least a portion of the data to provide modified data comprises performing graphics processing operations on the data.

3. The method of claim 1 , further comprising:

substantially concurrent with the reading and storing of data, updating second data previously stored in a second memory with a modified portion of the second data; and

substantially concurrent with the updating of the data, reading third data and storing the third data in the second memory.

4. The method of claim 1 , further comprising providing the data read from the location to an output bus for provision to a requesting entity.

5. The method of claim 1 wherein storing the data at a buffer location in a buffer memory comprises storing the data at a buffer location in a first-in-first-out (FIFO) buffer.

6. In a graphics processing system having a memory system including an embedded memory array and having error-correction coding, a method for accessing the embedded memory array, comprising:

reading first data and an associated error correction code from a first location corresponding to a first memory address in the embedded memory array;

storing the first data at a first buffer location in a first buffer memory having a plurality of buffer locations for storing a plurality of data;

substantially concurrent with the reading and storing of the first data in the first buffer memory,

logically combining second data previously stored at a second buffer location in a second buffer memory with modified data;

calculating a new error correction code based on the combined updated second data in the second buffer memory; and

storing the combined second data and the new error correction code to a second location corresponding to a second memory address in the embedded memory array from which the second data was originally read;

processing at least a portion of the first data to provide first modified data;

reading third data from a third location corresponding to a third memory address in the embedded memory array;

storing the third data at a third buffer location in the second buffer memory; and

substantially concurrent with the reading and storing of the third data,

logically combining the first data stored at the first buffer location in the first buffer memory with the first modified data;

calculating a new error correction code based on the combined updated first data in the first buffer memory; and

storing the combined first data and the new error correction code to the first location corresponding to the first memory address in the embedded memory array.

7. The method of claim 6 wherein processing at least a portion of the first data to provide first modified data comprises performing graphics processing operations on the first data.

8. The method of claim 6 , further comprising providing the first data to an output bus for provision to a requesting entity.

9. The method of claim 6 wherein storing the first data at a first buffer location in a first buffer memory comprises storing the first data at a first buffer location in a first-in-first-out (FIFO) buffer.

10. A memory system, comprising:

an embedded memory having a read data port and a write data port;

an error-correction code (EGG) generator coupled to the write data port and configured to generate an associated EGG for data written to the embedded memory;

an ECC check circuit coupled to the read data port and configured to confirm the integrity of the data based on the associated EGG;

a memory having an output coupled to the EGG generator and further having an input coupled to the EGG check circuit, the memory configured to store data read from the embedded memory and to store a memory address associated with the stored data, the memory further configured to output the stored data associated with a memory address in response to receiving the same;

a first selection circuit having an input coupled to the output of the memory, and a first output coupled to a read bus and a second output coupled to the EGG generator and the write data port;

a second selection circuit having an output, and further having a first input coupled to the EGG check circuit and a second input coupled to a write bus;

combination logic having an output coupled to the input of the memory, a first input coupled to the output of the memory and a second input coupled to the EGG check circuit, the combination logic configured to combine data applied to the first and second inputs and provide combined data at the output; and

a control circuit coupled to the first and second selection circuits, the memory, and the combination logic, the control circuit configured to control the first and second selection circuits and coordinate the storing of data from the embedded memory in the memory and provide the data to an output bus, and in response to receiving a write request, coordinate the combining of modified data received from the write bus with corresponding original data previously stored in the memory and further provide the combined data for EGG calculation and writing to the memory location in the embedded memory from where the original data was read.

11. The apparatus of claim 10 , further comprising:

a second memory an output coupled to the EGC generator and an input coupled to the EGG check circuit, the second memory configured to store data read from the embedded memory and to store a memory address associated with the stored data, the memory further configured to output the stored data associated with a memory address in response to receiving the same;

second combination logic having an output coupled to the second memory, a first input coupled to the output of the second memory, and a second input coupled to the EGG check circuit, the second combination logic configured to combine data applied to the first and second inputs and provide combined data at the output.

12. The apparatus of claim 11 , wherein the control circuit is further configured to coordinate the storing of data from the embedded memory in the second memory and provide the data to the output bus, and in response to receiving a write request, coordinate the combining of modified data received from the write bus with corresponding original data previously stored in the second memory and further provide the combined data for EGG calculation and writing to the memory location in the embedded memory from where the original data was read.

13. The apparatus of claim 10 wherein the memory comprises a static random access memory.

14. The apparatus of claim 10 wherein the embedded memory comprises a dual-port embedded memory.

15. The apparatus of claim 10 wherein the memory comprises a first-in-first-out (FIFO) buffer.