Method and apparatus for improving bus master performance
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.
1. In a computer-based system employing a CPU, a memory subsystem, and at least one bus master interface module, a method comprising:
monitoring a signal used to adaptively control a throttling of said CPU;
monitoring said CPU for a CPU power state;
monitoring said CPU for a CPU performance state; and
performing dynamic arbitration of memory accesses, by said CPU and said at least one bus master interface module, to said memory subsystem based on, at least in part, said monitorings.
2. The method of claim 1 further comprising monitoring bus master initiated memory access break events to aid in performing said dynamic arbitration.
3. The method of claim 1 further comprising monitoring pending memory read accesses to aid in performing said dynamic arbitration.
4. The method of claim 1 further comprising monitoring pending memory write accesses to aid in performing said dynamic arbitration.
5. The method of claim 1 wherein said signal is generated based on measuring CPU performance by running at least one of the known code segments run during boot time of said CPU, key processing performance parameters corresponding to pre-defined run-time segments of said CPU, a CPU percent idle value, a CPU time stamp, and statistically predicting how to throttle said CPU on a time segment by time segment basis.
6. The method of claim 5 wherein said signal comprises a STPCLK# signal that commands said CPU to begin processing when said STPCLK# signal is de-asserted (high) and commands said CPU to stop processing when said STPCLK# signal is asserted (low).
7. The method of claim 5 wherein said signal comprises a CPU throttle control signal that commands said CPU to begin processing when said CPU throttle control signal is de-asserted (high) and commands said CPU to stop processing when said CPU throttle control signal is asserted (low).
8. The method of claim 1 wherein said CPU power state comprises any one of ACPI-defined CPU power states.
9. The method of claim 1 wherein said CPU performance state comprises any one of ACPI-defined CPU performance states.
10. The method of claim 1 wherein said at least one bus master interface module comprises a graphics interface module.
11. The method of claim 1 wherein said at least one bus master interface module comprises a southbridge interface module.
12. In a computer-based system employing a CPU, a memory subsystem, and at least a first module, apparatus for performing dynamic arbitration of memory accesses to said memory subsystem, said apparatus comprising:
a second module to generate a signal indicating when said CPU is idle and to monitor and output CPU power states and CPU performance states;
a third module to perform dynamic arbitration of memory accesses, by said CPU and said at least a first module, to a memory based on, at least in part, said signal, said CPU power states and said CPU performance states; and
a fourth module to control accesses to said memory subsystem based on, at least in part, said dynamic arbitration.
13. The apparatus of claim 12 wherein said first module comprises a bus master interface module.
14. The apparatus of claim 12 wherein said second module comprises a CPU throttle control module.
15. The apparatus of claim 12 wherein said third module comprises an arbitration (ARB) module.
16. The apparatus of claim 12 wherein said fourth module comprises a memory controller (MC) module.
17. The apparatus of claim 12 wherein said signal comprises a CPU throttle control signal.
18. The apparatus of claim 12 wherein said at least one first module interfaces to said second module and said third module.
19. The apparatus of claim 12 wherein said at least one first module comprises an AGP graphics interface module interfacing between said fourth module and at least one AGP graphics device to generate at least one of a memory access break event, a bus master access request, and a memory read/write signal.
20. The apparatus of claim 12 wherein said at least one first module comprises a southbridge interface (SBRI) module interfacing between said fourth module and at least one of a southbridge device, a bus master device, and a DMA device to generate at least one of a memory access break event, a bus master access request, and a memory read/write signal.
21. The apparatus of claim 12 wherein said at least one first module interfaces between said fourth module and at least one of a PCI device, a PCI express device, or any bus master I/O device to generate at least one of a memory access break event, a bus master access request, and a memory read/write signal.
22. The apparatus of claim 16 wherein said memory controller (MC) module comprises:
a fifth module to detect any pending memory read/write accesses and perform memory row and memory bank decoding; and
a sixth module to control electrical interface signals and timing control signals, including memory power management signals, to at least one seventh module within said memory subsystem.
23. The apparatus of claim 22 wherein said fifth module comprises a read/write buffer controller module.
24. The apparatus of claim 22 wherein said sixth module comprises a DRAM controller module.
25. The apparatus of claim 22 wherein said seventh module comprises a DRAM module.
26. The apparatus of claim 12 wherein said signal is generated based on at least one of CPU performance of known code segments run during a boot time of said CPU, key processing performance parameters corresponding to pre-defined run-time segments of said CPU, a CPU percent idle value, a CPU time stamp, and statistically predicting how to throttle said CPU on a time segment by time segment basis.
27. The apparatus of claim 12 wherein said signal comprises a STPCLK# signal that commands said CPU to begin processing when said STPCLK# signal is de-asserted (high) and commands said CPU to stop processing when said STPCLK# signal is asserted (low).
28. The apparatus of claim 12 wherein said CPU power states comprise ACPI-defined CPU power states.
29. The apparatus of claim 12 wherein said CPU performance states comprise ACPI-defined CPU performance states.