Voltage level shifting circuit
The voltage level shifting circuit includes a complimentary signal input circuit having a pair of MOSs of a first withstand voltage and a load circuit having a pair of MOSs of a second withstand voltage, a first voltage down-converting element which prevents a potential level exceeding the first withstand voltage from being supplied to a complementary signal input circuit, and a third MOS of the second withstand voltage electrically connecting a third power supply node to an output node responsive to a voltage potential from the load circuit. The voltage level shifting circuit also includes a fourth MOS of the first withstand voltage electrically connecting a first power supply node to the output node responsive to one of the voltage potentials of the complimentary signal, and a second voltage down-converting element which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS.
1. A voltage level shifting circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third power supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage down-converting circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, which has a gate directly coupled to one of the complimentary signals, and which electrically connects the first power supply node to the output node in response to a voltage potential of the one of the complimentary signals; and
a second voltage down-converting circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor.
2. The voltage level shifting circuit according to claim 1 , wherein the first voltage down-converting circuit comprises a pair of fifth MOS transistors, each of which has a first electrode coupled to the load circuit, a second electrode coupled to the corresponding second electrodes of the first MOS transistors, and a gate electrode supplied with a fixed voltage potential level.
3. The voltage level shifting circuit according to claim 2 , wherein the fixed voltage potential level is the second power supply potential level.
4. The voltage level shifting circuit according to claim 1 , wherein the second voltage down-converting circuit comprises a sixth MOS transistor which has a first electrode coupled to the third MOS transistor, a second electrode coupled to the fourth MOS transistor, and a gate electrode supplied with a fixed voltage potential level.
5. The voltage level shifting circuit according to claim 4 , wherein the fixed voltage potential level is the second power supply potential level.
6. A voltage level shifting circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third power supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage down-converting circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, and which electrically connects the first power supply node to the output node in response to one of voltage potentials of the complimentary signals; and
a second voltage down-converting circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor,
wherein the pair of second MOS transistors constitute a current mirror load.
7. A voltage level shifting circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third power supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage down-converting circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, and which electrically connects the first power supply node to the output node in response to one of voltage potentials of the complimentary signals;
a second voltage down-converting circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor; and
a constant current element which is coupled between the first electrodes of the first MOS transistors and the first power supply node.
8. The voltage level shifting circuit according to claim 7 , wherein the constant current element comprises a MOS transistor.
9. A voltage level shift circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third power supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage descending circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, which has a gate directly coupled ot one of the complimentary signals, and which electrically connects the first power supply node to the output node in response to the voltage potential of the one of the complimentary signals; and
a second voltage descending circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor.
10. The voltage level shifting circuit according to claim 9 , wherein the first voltage descending circuit comprises a pair of fifth MOS transistors, each of which has a first electrode coupled to the load circuit, a second electrode coupled to the corresponding second electrodes of the first MOS transistors, and a gate electrode supplied with a fixed voltage potential level.
11. The voltage level shift circuit according to claim 10 , wherein the fixed voltage potential level is the second power supply potential level.
12. The voltage level shift circuit according to claim 9 , wherein the second voltage descending circuit comprises a sixth MOS transistor which has a first electrode coupled to the third MOS transistor, a second electrode coupled to the fourth MOS transistor, and a gate electrode supplied with a fixed voltage potential level.
13. The voltage level shift circuit according to claim 12 , wherein the fixed voltage potential level is the second power supply potential level.
14. A voltage level shift circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third power supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage descending circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, and which electrically connects the first power supply node to the output node in response to one of voltage potentials of the complimentary signals; and
a second voltage descending circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor,
wherein the pair of second MOS transistors constitute a current mirror load.
15. A voltage level shift circuit comprising:
a first power supply node supplied with a first power supply potential level;
a second power supply node supplied with a second power supply potential level higher than the first power supply potential level;
a third cower supply node supplied with a third power supply potential level higher than the second power supply potential level;
a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels;
a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals;
a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode;
a first voltage descending circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit;
a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit;
a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, and which electrically connects the first power supply node to the output node in response to one of voltage potentials of the complimentary signals;
a second voltage descending circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor; and
a constant current element which is coupled between the first electrodes of the first MOS transistors and the first power supply node.
16. The voltage level shift circuit according to claim 15 , wherein the constant current element comprises a MOS transistor.