Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
An integrated circuit is disclosed which includes a variety of NDR devices having different characteristics. The different NDR devices are formed to have different PVRs, different onset NDR voltages, etc. in a common substrate, by controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like.
1. A method of forming negative differential resistance (NDR) devices on a substrate, comprising the steps of:
forming a first silicon-based NDR device having a first NDR characteristic on a first portion of the substrate; and
forming a second silicon-based NDR device having a second NDR characteristic on a second portion of the substrate; and
wherein said first NDR characteristic and said second NDR characteristic are substantially different and are used in a first silicon based processing circuit and a separate second silicon based processing circuit respectively.
2. The method of claim 1 wherein said first NDR characteristic includes a first peak-to-valley ratio (PVR), and said second NDR characteristic includes a second PVR, such that said first PVR is substantially greater than said second PVR.
3. The method of claim 1 wherein said first NDR characteristic includes a first onset voltage (VNDR 1 ) for an NDR operating region, and said second NDR characteristic includes a second onset voltage (VNDR 2 ) for an NDR operating region, where VNDR 1 is less than VNDR 2 .
4. The method of claim 1 wherein said first silicon based processing circuit corresponds to a logic circuit and said second silicon based processing circuit corresponds to a memory circuit.
5. The method of claim 1 wherein said first silicon based processing circuit operates at a first frequency and said second silicon based processing circuit operates at a second frequency greater than said first frequency.
6. The method of claim 1 wherein said first silicon based processing circuit corresponds to a first memory circuit operating with a first operating power requirement and said second silicon based processing circuit corresponds to a second memory circuit operating at a second operating power requirement that is greater than said first operating power requirement.
7. The method of claim 1 wherein said first silicon-based NDR device is a first field effect transistor (FET) with a first voltage threshold and a first gate length, and said second silicon-based NDR device is a second FET with a second voltage threshold and a second gate length that are substantially different from said first voltage threshold and said first gate length respectively.
8. The method of claim 1 wherein said first silicon based processing circuit operates at a first average activity factor and said second silicon based processing circuit operates at a second average activity factor greater than said first average activity factor.
9. The method of claim 1 , wherein said first NDR characteristic and said second NDR characteristic result from a first trap distribution and a second charge trap distribution formed for said first silicon-based NDR device and said second silicon-based NDR device respectively.
10. The method of claim 9 , wherein said first trap distribution is formed by a first mask and a first impurity implantation into a first NDR region, and said second charge trap distribution is formed by a second mask and a second impurity implantation into a second NDR region.
11. A method of forming a negative differential resistance (NDR) device comprising the steps of:
(a) forming a first gated silicon-based NDR element and a second gated silicon-based NDR element;
(b) setting a peak-to-valley ratio (PVR) characteristic of said first gated silicon-based NDR element to a first target PVR value;
(c) setting a PVR characteristic of said second gated silicon-based NDR element to a second target PVR value;
wherein said first PVR value and said second PVR value are set to different values during manufacturing of the NDR device to provide different NDR characteristics for said first gated silicon-based NDR element and said second gated silicon-based NDR element.
12. The method of claim 11 wherein said first PVR value and said second PVR value differ by at least 50%.
13. The method of claim 12 wherein said first PVR value and said second PVR value differ by at least 100%.
14. The method of claim 11 wherein said first PVR value is at least 10 times said second PVR value.
15. The method of claim 11 wherein said first NDR element is used in a memory circuit, and said second NDR element is used in a logic circuit.
16. The method of claim 11 , wherein said first gated silicon-based NDR element and said second gated silicon-based NDR element are formed using metal oxide semiconductor (MOS) compatible processing operations.
17. A method of operating different types of negative differential resistance (NDR) devices in an integrated circuit, comprising the steps of:
operating a first circuit in the integrated circuit using a first silicon-based NDR device having a first NDR characteristic; and
operating a second circuit in the integrated circuit using a second silicon-based NDR device having a second NDR characteristic; and
wherein said first NDR characteristic and said second NDR characteristic are substantially different so that said first circuit and said second circuit are caused to operate with substantially different electrical characteristics.
18. The method of claim 17 , wherein said substantially different electrical characteristics include a first clock frequency used by said first circuit and a second clock frequency used by said second circuit, and such that said first clock frequency and said second clock frequency are substantially different clock frequencies.
19. The method of claim 17 , wherein said substantially different electrical characteristics include a first gate bias voltage used by said first circuit and a second gate bias voltage used by said second circuit, and such that said first gate bias and said second gate bias are substantially different voltages.
20. The method of claim 17 , wherein said substantially different electrical characteristics include a first current level used by said first circuit and a second current level used by said second circuit, and such that said first current level and said second current level are substantially different currents.
21. A semiconductor based circuit comprising:
a first silicon-based NDR device having a first NDR characteristic on a first portion of a substrate of the semiconductor based circuit; and
a second silicon-based NDR device having a second NDR characteristic on a second portion of said substrate; and
wherein said first NDR characteristic and said second NDR characteristic are substantially different and are used in a first silicon based processing circuit and a separate second silicon based processing circuit respectively on the semiconductor based circuit.
22. The semiconductor based circuit of claim 21 , wherein said first NDR characteristic is provided by tailoring a first charge trapping region associated with said first silicon-based NDR device.
23. The semiconductor based circuit of claim 21 , wherein said second NDR characteristic is provided by tailoring a second charge trapping region associated with said second silicon-based NDR device.
24. The semiconductor based circuit of claim 21 , wherein at least one of said first silicon-based NDR device and said second silicon-based NDR device is an NDR FET.
25. The semiconductor based circuit of claim 21 , wherein at least one of said first silicon-based NDR device and said second silicon-based NDR device is a tunnel diode.
26. The semiconductor based circuit of claim 21 , wherein said first NDR characteristic and said second NDR characteristic correspond to a first peak-to-valley ratio (PVR) and a second PVR respectively.
27. The semiconductor based circuit of claim 21 , wherein said first NDR characteristic and said second NDR characteristic correspond to a first peak- or valley-current value and a second current peak- or valley-current value respectively.
28. The semiconductor based circuit of claim 21 , wherein said first NDR characteristic and said second NDR characteristic are caused by a first operating frequency and a second operating frequency respectively.
29. The semiconductor based circuit of claim 21 wherein said first silicon based processing circuit corresponds to a memory circuit and said second silicon based processing circuit corresponds to a logic circuit.
30. The semiconductor based circuit of claim 21 wherein said first silicon-based NDR device is an NDR FET with a first gate length, and said second silicon-based NDR device is an NDR FET having a second gate length that is substantially different from said first gate length.
31. The semiconductor based circuit of claim 21 wherein said first silicon-based NDR device is an NDR FET with a first gate insulator thickness, and said second silicon-based NDR device is an NDR FET having a second gate insulator thickness that is substantially different from said first gate thickness.
32. The semiconductor based circuit of claim 21 wherein said first portion of said substrate and said second portion of said substrate are located in a common region, and such that said first silicon-based NDR device and said second silicon-based NDR share one or more common layers and/or one or more common diffusion areas.