Charge trapping device and method of forming the same
A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.
1. A silicon based field effect transistor (FET) comprising:
trapping layer proximate to transistor channel region for the FET, said trapping layer including a carrier trapping sites configured for trapping and detrapping carriers from said channel region;
said carrier trapping sites being distributed such that a concentration of said carrier trapping sites in a bulk region of said trapping layer is at least one order of magnitude less than it is along an interface with said transistor channel region;
wherein the FET can exhibit negative differential resistance as a result of said trapping and de-trapping of carriers.
2. The silicon based FET of claim 1 , wherein said a concentration of said carrier trapping sites at said interface per cubic centimeter is at least two orders of magnitude greater than a concentration of said carrier trapping sites within said bulk region of said trapping layer.
3. The silicon based FET of claim 1 , wherein a concentration of an impurity per cubic centimeter used for said carrier trapping sites is at least two times higher at a trapping layer-channel interface than in said channel region.
4. The silicon based FET of claim 3 , wherein said impurity is Boron.
5. The silicon based FET of claim 1 , wherein said carrier trapping sites include two different types of impurities.