Circuit arrangement for generating a digital clock signal
A circuit arrangement for generating a digital clock signal which manages without a crystal oscillator and has a low current consumption. The circuit arrangement includes: a transistor circuit having a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series, a comparator having a positive comparator input, a negative comparator input and a comparator output, a device for providing two switching thresholds to the negative input of the comparator, and a capacitance, which is alternately charged and discharged via the two FET transistors. The voltage present at the capacitance is fed to the positive comparator input, and the output voltage of the comparator, which represents a digital clock signal, is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors.
1. A circuit arrangement for generating a digital clock signal, the circuit arrangement comprising:
a transistor circuit including a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series,
a comparator including a positive comparator input, a negative comparator input and a comparator output,
a device for providing two switching thresholds, which, at its output, alternatively provides the two switching thresholds to the negative input of the comparator,
a capacitance, which is alternately charged and discharged via the two FET transistors, the voltage present at the capacitance being fed to the positive comparator input,
means for setting a frequency of the digital clock signal generated by the comparator by influencing the voltage at the positive comparator input,
wherein an output signal generated at the output terminal of the comparator represents a digital clock signal, which is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors,
wherein the means for setting the frequency comprises a device for controlling currents respectively passing through the first FET transistor and the second FET transistor, and
wherein the device for controlling currents includes means for controlling the first FET transistor and the second FET transistor such that the capacitance is continuously charged discharged via the first FET transistor and the second FET transistor.
2. The circuit arrangement as claimed in claim 1 , further comprising:
a first current source for providing a current for the first FET transistor, and
a second current source for providing a current through the second FET transistor,
wherein the device for controlling the currents comprises means for controlling the first current source and the second current source.
3. The circuit arrangement as claimed in claim 1 , wherein the means for setting the frequency further comprises a device for setting a magnitude of the capacitance.
4. The circuit arrangement as claimed in claim 3 , wherein the capacitance comprises a plurality of partial capacitances and a plurality of switches for selectively connecting the partial capacitances in parallel with one another, and wherein the device for setting the magnitude of the capacitance controls the plurality of switches to connect the partial capacitances according to a selected frequency.
5. The circuit arrangement as claimed in claim 3 , wherein the device for setting the magnitude of the capacitance comprises means for performing a comparison of a present frequency of the digital clock signal with a reference frequency at predetermined time intervals.
6. The circuit arrangement as claimed in claim 1 , wherein the device for controlling the currents through the first FET transistor and the second FET transistor comprises means for performing a comparison of a present frequency of the digital clock signal with a reference frequency at predetermined time intervals.
7. The circuit arrangement as claimed in claim 1 , wherein the currents through the first FET transistor and the second FET transistor have identical magnitudes.
8. The circuit arrangement as claimed in claim 1 , wherein the first FET transistor and the second FET transistor are designed in complementary fashion with respect to one another.
9. The circuit arrangement as claimed in claim 1 , wherein the device for providing two switching thresholds comprises an inverter, whose input is clocked by the digital clock signal.
10. The circuit arrangement as claimed in claim 1 , wherein the individual components being embodied in CMOS technology.
11. A digital clock circuit comprising:
a comparator having a first input terminal, a second input terminal, and an output terminal;
an inverter having an input terminal connected to the output terminal of the comparator and an output terminal connected to the first input terminal of the comparator;
a p-channel field-effect transistor (FET) having a first terminal coupled to a first voltage source, a second terminal connected to the second input terminal of the comparator, and a gate terminal connected to the output terminal of the comparator;
an n-channel field-effect transistor (FET) having a first terminal coupled to a second voltage source, a second terminal connected to the second input terminal of the comparator, and a gate terminal connected to the output terminal of the comparator;
a capacitance circuit connected to the second input terminal of the comparator; and
means for controlling currents respectively passing through the p-channel FET and the n-channel FET such that the capacitance circuit is continuously charged discharged via the p-channel FET and the n-channel FET.
12. The digital clock circuit according to claim 11 , wherein the comparator comprises an operational amplifier, the first input terminal comprises an inverting input of the operational amplifier, and the second terminal comprises a non-inverting input of the operational amplifier.
13. The digital clock circuit according to claim 11 , wherein the inverter comprises a p-channel transistor connected in series with an n-channel transistor between a high voltage source and a low voltage source, wherein the gate terminals of the p-channel transistor and the n-channel transistors are connected to the output terminal of the comparator.
14. The digital clock circuit according to claim 11 , wherein the means for controlling currents comprises:
a first current source connected between the first voltage source and the first terminal of the p-channel FET; and
a second current source connected between the second voltage source and the first terminal of the n-channel FET.
15. The digital clock circuit according to claim 14 , further comprising means for comparing a frequency of a digital clock signal generated an the output terminal of the comparator with a reference frequency, and f or controlling at least one of a capacitance magnitude of the capacitance circuit, a current magnitude of the first current source, and a current magnitude of the second current source such that the digital clock signal frequency is equal to the reference frequency.
16. The digital clock circuit according to claim 11 , wherein the capacitance circuit comprises:
a first capacitor connected between the second input terminal of the comparator and the second voltage source;
a second capacitor having a first terminal connected to the second voltage source and a second terminal; and
a switch connected between the second terminal of the second capacitor and the second input terminal of the comparator.
17. The digital clock circuit according to claim 16 , further comprising means for comparing a frequency of a digital clock signal generated an the output terminal of the comparator with a reference frequency, and for controlling the switch to change a capacitance magnitude of the capacitance circuit such that the digital clock signal frequency is equal to the reference frequency.
18. The digital clock circuit according to claim 16 , further comprising a CMOS element including the p-channel FET and the n-channel FET.