Granted Patent B2

US 7,071,050 · App. 11/220,723 · Granted Jul 4, 2006

Assignee: Hitachi, Ltd.

Abstract

Claims (98)

1. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a (i) first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, a control gate electrode of said first MISFET formed on said second gate insulating film, and with a (ii) third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposite to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate; and

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region,

wherein a junction depth of said third semiconductor region is greater than that of a junction depth of said first semiconductor region,

wherein a dose introduced in said step (e) is higher than the dose in said step (b);

(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate; and

(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,

wherein said fourth semiconductor region serves as a drain region of said second MISFET.

2. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of second conductivity type, opposed to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate; and

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor regions,

wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and

wherein a dose introduced in said step (e) is higher than the dose in said step (e);

(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate; and

(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,

wherein said fourth semiconductor region serves as a drain region of said second MISFET.

3. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate; and

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region;

wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and

wherein a dose introduced in said step (e) is higher than the dose in said step (b); and

(g) after said step (f), forming side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode.

4. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate; and

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor regions,

wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and

wherein a dose introduced in said step (e) is higher than the dose in said step (b); and

(g) after said step (f), forming side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode.

5. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET or a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region,

wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and

wherein a dose introduced in said step (e) is higher than the dose in said step (b);

(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate; and

(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode,

wherein said fourth semiconductor region serves as a drain region of said second MISFET.

6. A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;

(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;

(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;

(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;

(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate; and

(f) after said step (e), performing a heat treatment to form said third semiconductor region,

wherein said second semiconductor region is formed under said first semiconductor region,

wherein a channel forming region of said first MISFET is formed between said first semiconductor regions;

wherein a junction depth of said third semiconductor region is greater than that of a junction depth of said first semiconductor region,

wherein a dose introduced in said step (e) is higher than the dose in said step (b);

(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate; and

(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,

wherein said fourth semiconductor region serves as a drain region of said second MISFET.

7. A method of manufacturing a semiconductor memory device according to claim 1 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

8. A method of manufacturing a semiconductor memory device according to claim 2 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

9. A method of manufacturing a semiconductor memory device according to claim 3 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

10. A method of manufacturing a semiconductor memory device according to claim 4 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

11. A method of manufacturing a semiconductor memory device according to claim 5 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

12. A method of manufacturing a semiconductor memory device according to claim 6 ,

wherein said step (b) is performed after said step (a), and

wherein said step (c) is performed after said step (a).

Assignments (2)

Priority Claims (1)

Continuity (10)