IP Library › Granted Patent US 7,103,055
Granted Patent B2
US 7,103,055 · App. 10/173,414 · Granted Sep 5, 2006

Unified table for L2, L3, L4, switching and filtering

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 7,103,055
App. No.
10/173,414
Granted
Sep 5, 2006
Kind
B2
Abstract

A network switch for network communications, wherein the network switch includes at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate. The at least one data port interface includes an ingress logic circuit in communication with the at least one data port interface for generating at least one of an ingress address resolution and a filtering search request. A CPU interface is provided and configured to communicate with a CPU. A shared hierarchical memory structure including an internal memory in communication with the at least one data port interface, and an external memory in communication with a memory management unit via an external memory interface is provided. A communication channel is provided for communicating data between the at least one data port interface, the internal memory, the CPU interface, and the memory management unit. Additionally, a unified table is provided, wherein the unified table is in connection with the communication channel, and the at least one data port interface. The unified table contains packet handling data for the network switch.

Claims (61)

1. A network switch for network communications, said network switch comprising:

at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate, said at least one data port interface including an ingress logic circuit in communication with said at least one data port interface for generating at least one of an ingress address resolution and a filtering search request;

a CPU interface, said CPU interface configured to communicate with a CPU;

a shared hierarchical memory structure, wherein said shared hierarchical memory structure includes an internal memory in communication with the at least one data port interface, and an external memory in communication with a memory management unit via an external memory interface;

a communication channel, said communication channel for communicating data between said at least one data port interface, said internal memory, said CPU interface, and said memory management unit, and

a unified table, said unified table being in connection with the communication channel, and the at least one data port interface, said unified table containing packet handling data for the network switch comprising address resolution information including L 2 information, L 3 information, and L 4 information.

2. A network switch as recited in claim 1 , wherein said unified table further comprises a single table having both said address resolution information and filtering information stored therein.

3. A network switch as recited in claim 1 , wherein said unified table further comprises a single table of a predetermined size.

4. A network switch as recited in claim 1 , wherein said unified table further comprises:

a single table having both address resolution and filtering information therein; and

a unified table logic circuit, said unified table logic circuit in connection with said single table,

wherein said unified table logic circuit is configured to receive the search request from the at least one data port interface and convert the search request into unified table form.

5. A network switch for network communications, said network switch comprising:

at least one data port interface supporting a plurality of data ports, said at least one data port interface including an ingress logic circuit in communication with said at least one data port interface for generating an ingress address resolution and filtering search request;

a unified table having a table logic circuit in communication therewith, said table logic circuit being in communication with the at least one data port interface,

wherein the table logic circuit receives the search request from the ingress logic circuit and searches the unified table for an entry desired by the search request; and

wherein the unified table contains address resolution information including L 2 address resolution information, L 3 address resolution information and L 4 address resolution information.

6. A network switch for network communications as recited in claim 5 , wherein said unified table further comprises a single table having both said address resolution information and filtering action information therein.

7. A network switch for network communications as recited in claim 6 , wherein said unified table is further configured to vary the predetermined quantities of L 2 address information, L 3 address information, L 4 address resolution information, and filtering action information.

8. A network switch for network communications as recited in claim 7 , wherein the unified table is configured to vary the predetermined quantities during switch operation in accordance with spatial demands.

9. A network switch for network communications as recited in claim 5 , wherein said unified table is configured to receive L 2 address resolution information, L 3 address resolution information, L 4 address resolution information, and filtering action information.

10. A method for conducting address resolution and filtering in a network switch, said method comprising the steps of:

receiving a packet on a port of a network switch;

generating a search request for address resolution of the packet;

searching a unified table having both address resolution information and filtering information therein with the search request to determine if a match to the search request is in the unified table;

determining if the unified table contains the match to the search request; and

generating a search response in accordance with an outcome of the determination;

wherein the address resolution information comprises address resolution information including L 2 information, L 3 information, and L 4 information.

11. A method for conducting address resolution and filtering in a network switch as recited in claim 10 , wherein generating the search request further comprises:

generating an address resolution search request in a port address resolution logic circuit;

receiving the address resolution search request in a unified table logic circuit; and

converting the search request into a unified table formatted search request.

12. A method for conducting address resolution and filtering in a network switch as recited in claim 11 , wherein said converting step further comprises the steps of:

determining a request opcode for the search request, said request opcode representing a type of address resolution request; and

constructing a key for searching in the unified table,

wherein said key is constructed from the request opcode and a search key received from the port address resolution logic circuit.

13. A method for conducting address resolution and filtering in a network switch as recited in claim 11 , wherein said step of searching the unified table further comprises searching the unified table with the unified table formatted search request.

14. A method for conducting address resolution and filtering in a network switch as recited in claim 13 , wherein said step of generating a search response further comprises generating the search response with the unified table logic circuit and forwarding the search response to the port address resolution circuit.

15. A method for conducting address resolution and filtering in a network switch as recited in claim 10 , wherein said method further comprises the step of generating a search request for filtering of the packet.

16. A method for conducting address resolution and filtering in a network switch as recited in claim 15 , wherein said search request for filtering and said search request for address resolution are forwarded to a unified table logic circuit for processing.

17. A network communications device comprising:

at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate, said at least one data port interface including an ingress logic circuit in communication with said at least one data port interface for generating at least one of an ingress address resolution and a filtering search request;

a CPU interface, said CPU interface configured to communicate with a CPU;

a memory structure in communication with the at least one data port interface;

a communication channel communicating data between said at least one data port interface, said memory structure, and said CPU interface; and

a unified table, said unified table being in connection with the communication channel, and the at least one data port interface, said unified table containing packet handling data for the network switch comprising address resolution information including L 2 information, L 3 information, and L 4 information.

18. A network communications device as recited in claim 17 , wherein said unified table further comprises a single table having both said address resolution information and filtering information stored therein.

19. A network communications device as recited in claim 17 , wherein said unified table further comprises a single table of a predetermined size.

20. A network communications device as recited in claim 17 , wherein said network communications device comprises a single switch on chip.

21. A network communications device as recited in claim 17 , wherein said network communications device comprises a switch fabric used to provide communication between network devices.

22. A method for conducting address resolution and filtering in a network communications device as recited in claim 17 , wherein said network communications device comprises a single switch on chip.

23. A method for conducting address resolution and filtering in a network communications device as recited in claim 17 , wherein said network communications device comprises a switch fabric used to provide communication between network devices.

24. A method for conducting address resolution and filtering in a network communications device, said method comprising the steps of:

receiving a packet on a port of a network communications device;

generating a search request for address resolution of the packet;

searching a unified table having both address resolution information and filtering information therein with the search request to determine if a match to the search request is in the unified table;

determining if the unified table contains the match to the search request; and

generating a search response in accordance with an outcome of the determination;

wherein the address resolution information comprises address resolution information including L 2 information, L 3 information, and L 4 information.

25. A method for conducting address resolution and filtering in a network communications device as recited in claim 24 , wherein said method further comprises the step of generating a search request for filtering of the packet.

26. A method for conducting address resolution and filtering in a network communications device as recited in claim 24 , wherein said search request for filtering and said search request for address resolution are forwarded to a unified table logic circuit for processing.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
Continuity (6)
Continuation 0961948800 · Jul 19, 2000
Continuation In Part 0934340900 · Jun 30, 1999
Provisional Application 6014507600 · Jul 21, 1999
Provisional Application 6009597200 · Aug 10, 1998
Provisional Application 6009222000 · Jul 8, 1998
Related Publication 20020186705A1 · Dec 12, 2002