Strained-semiconductor-on-insulator finFET device structures
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
1. A structure comprising:
a substrate having a dielectric layer disposed thereon; and
a fin-field-effect transistor disposed over the substrate, the fin-field-effect-transistor including:
a source region and a drain region disposed in contact with the dielectric layer, the source and the drain regions comprising a strained semiconductor material;
at least one fin extending between the source and the drain regions, the fin consisting essentially of a strained semiconductor material;
a gate disposed above the strained semiconductor layer, extending over at least one fin and between the source and the drain regions; and
a gate dielectric layer disposed between the gate and the fin.
2. The structure of claim 1 , wherein the fin comprises at least one of a group II, a group III, a group IV, a group V, or a group VI element.
3. The structure of claim 1 , wherein the strained semiconductor layer is tensilely strained.
4. The structure of claim 3 , wherein the strained semiconductor layer comprises tensilely strained silicon.
5. The structure of claim 1 , wherein the strained semiconductor layer is compressively strained.
6. The structure of claim 5 , wherein the strained semiconductor layer comprises compressively strained germanium.
7. The structure of claim 1 , wherein at least one of the source and drain regions comprises a silicide.
8. The structure of claim 1 , wherein at least one of the source and drain regions comprises a raised region.
9. The structure of claim 1 , wherein the at least one fin comprises a channel region.
10. The structure of claim 9 , wherein at least a portion of the channel region falls in a plane substantially perpendicular to a surface of the substrate.
11. The structure of claim 1 , wherein the gate dielectric comprises a high-k dielectric.
12. The structure of claim 1 , wherein the gate dielectric comprises silicon dioxide.
13. The structure of claim 1 , wherein the gate comprises a metal silicide.
14. The structure of claim 13 , wherein the gate comprises nickel silicide.
15. The structure of claim 1 , wherein the strained semiconductor material of the fin is bonded to the dielectric layer disposed on the substrate.