Method for forming self-aligned dual salicide in CMOS technologies
View Patent ↗A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
1. A method of fabricating a complementary metal oxide semiconductor (CMOS) device, said method comprising:
forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device;
forming a second well region in said semiconductor substrate for accommodation of a second type semiconductor device;
shielding said first type semiconductor device with a mask;
depositing a first metal layer over said second type semiconductor device;
performing a first salicide formation on said second type semiconductor device;
removing said mask;
depositing a second metal layer over the first and second type semiconductor devices; and
performing a second salicide formation on said first type semiconductor device,
wherein the first and second salicide formations are different from one another, and
wherein the sheet resistance in said CMOS device during the first and second salicide formations remains substantially constant.
2. The method of claim 1 , further comprising removing said second metal layer from said second type semiconductor device.
3. The method of claim 1 , wherein said first well region is configured as a NFET (N-type field effect transistor) well region and said second well region is configured as a PFET (P-type field effect transistor) well region.
4. The method of claim 1 , wherein said first well region is configured as a PFET (P-type field effect transistor) well region and said second well region is configured as a NFET (N-type field effect transistor) well region.
5. The method of claim 1 , wherein said first metal layer is formed of different materials than said second metal layer.
6. The method of claim 1 , wherein said first type semiconductor device is formed by:
configuring an insulator layer over said first well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said first well region.
7. The method of claim 1 , wherein said second type semiconductor device is formed by:
configuring an insulator layer over said second well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said second well region.
8. The method of claim 1 , further comprising forming a cap layer over each of said first metal layer and said second metal layer.
9. The method of claim 8 , wherein said cap layer comprises any of TiN, Ti, and TaN.
10. The method of claim 1 , wherein said first metal layer and said second metal layer comprises any of Ti, Co, Ni, Pt, Re, W, Pd, Ta, Nb, and their alloys.
11. A method of fabricating a complementary metal oxide semiconductor (CMOS) device comprising only one lithography level, said method comprising:
forming a first and second well region in a semiconductor substrate for accommodation of a respective first type and second type semiconductor device;
shielding said first type semiconductor device;
depositing a first metal layer over said second type semiconductor device;
performing a first salicide formation on said second type semiconductor device;
removing said shield;
depositing a second metal layer over the first and second type semiconductor devices; and
performing a second salicide formation on said first type semiconductor device,
wherein the first and second salicide formations are different from one another.
12. The method of claim 11 , further comprising removing said secomi metal layer from said second type semiconductor device.
13. The method of claim 11 , wherein said first well region is configured as a NFET (N-type field effect transistor) well region and said second well region is configured as a PFET (P-type field effect transistor) well region.
14. The method of claim 11 , wherein said first well region is configured as a PFET (P-type field effect transistor) well region and said second well region is configured as a NFET (N-type field effect transistor) well region.
15. The method of claim 11 , wherein said first metal layer is formed of different materials than said second metal layer.
16. The method of claim 11 , wherein said first type semiconductor device is formed by:
configuring an insulator layer over said first well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said first well region.
17. The method of claim 11 , wherein said second type semiconductor device is formed by:
configuring an insulator layer over said second well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said second well region.
18. The method of claim 11 , further comprising forming a cap layer over each of said first metal layer and said second metal layer.
19. The method of claim 18 , wherein said cap layer comprises any of TiN, Ti, and TaN.
20. The method of claim 11 , wherein said first metal layer and said second metal layer comprises any of Ti, Co. Ni, Pt, Re, W, Pd, Ta, Nb, and their alloys.