IP Library Granted Patent US 7,117,587
Granted Patent B2
US 7,117,587 · App. 10/655,223 · Granted Oct 10, 2006

Method for fabricating a substrate, including a plurality of chip package substrates

Assignee: Lite-On Semiconductor Corp.
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Quick Facts
Patent No.
US 7,117,587
App. No.
10/655,223
Granted
Oct 10, 2006
Kind
B2
Abstract

A method for fabricating a substrate, which includes a plurality of chip package substrates. One combined PCB includes a multi-layer rigid PCB and a soft PCB. The multi-layer rigid PCB is fixed on the soft PCB. At least one grooves or a pair is formed on an upper surface of the multi-layer rigid PCB. A portion of the multi-layer rigid PCB between the grooves is milled to expose a corresponding portion of the soft PCB to define an exposed area. The combined PCB is drilled through along two opposite sides of the grooves and the corresponding exposed area of the soft PCB. Breakable parts are formed at a center of the corresponding portion of the soft PCB and two opposite outside edges of the grooves.

Claims (8)

1. A method for fabricating a substrate, said substrate including a plurality of chip package substrates, comprising the steps of:

providing one combined PCB, including a soft PCB and a multi-layer rigid PCB fixed on a top surface of said soft PCB;

forming at least one groove on an upper surface of said multi-layer rigid PCB;

milling a portion of said multi-layer rigid PCB between said at least one groove for exposing a corresponding portion of said soft PCB to define an exposed area;

drilling through said combined PCB along two opposite sides of said at least one groove and said corresponding exposed area of said soft PCB; and

forming breakable parts at a center of said corresponding portion of said soft PCB and two opposite outside edges of said at least one groove.

2. The method for fabricating a substrate according to claim 1 , wherein said at least one pair of groove are formed by milling.

3. The method for fabricating a substrate according to claim 1 , further comprising the step of breaking said breakable parts to separate said chip package substrates.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2015
From: LITE-ON SEMICONDUCTOR CORP.
To: DYNA IMAGE CORPORATION
Reel/Frame 035117/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2003
From: CHEN, HUEI-JEN; LIU, EVAN; CHEN, YVON
To: LITE-ON SEMICONDUCTOR CORP.
Reel/Frame 014486/0994 →
Priority Claims (1)
TW 92118123 A · Jul 2, 2003 · national
Continuity (1)
Related Publication 20050001278A1 · Jan 6, 2005