IP Library Granted Patent US 7,119,362
Granted Patent B2
US 7,119,362 · App. 10/326,663 · Granted Oct 10, 2006

Method of manufacturing semiconductor apparatus

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,119,362
App. No.
10/326,663
Granted
Oct 10, 2006
Kind
B2
Abstract

In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.

Claims (39)

1. A test apparatus of a semiconductor apparatus, comprising:

a substrate provided with a projection formed on one main surface of said substrate so as to be electrically connectable to an electrode of a tested semiconductor apparatus, wherein said substrate is made of silicon;

a pad formed on a back surface side of said one main surface; and

a conductive member electrically connecting said projection and said pad,

wherein a region of said substrate where the projection is formed is deformed more easily than a region apart therefrom.

2. A test apparatus of a semiconductor apparatus according to claim 1 , wherein a substrate thickness of the region where said projection is formed is thinner than a substrate thickness of a region apart therefrom.

3. A test apparatus of a semiconductor apparatus according to claim 1 , wherein a number of tested conductor portions formed in a tested range of said substrate of said tested semiconductor apparatus is equal to a number of said projections which are formed in said substrate of said test apparatus and electrically independent.

4. A test apparatus of a semiconductor apparatus according to claim 1 , wherein said substrate is provided with a plurality of said projections, and a through groove crossing a line connecting two adjacent projections is formed in said substrate.

5. A test apparatus of a semiconductor apparatus according to claim 1 , wherein said one main surface of said substrate is provided with a region which is in contact with said tested semiconductor apparatus, in addition to said projection being in contact with said tested semiconductor apparatus, at a time of testing said tested semiconductor apparatus.

6. A test apparatus of a semiconductor apparatus according to claim 2 , wherein said region of said substrate where the projection is formed is constituted by a beam.

7. A test apparatus of a semiconductor apparatus, comprising:

a substrate provided with a projection formed on one main surface of said substrate so as to be electrically connectable to an electrode of a tested semiconductor apparatus;

a pad formed on a back surface side of said one main surface; and

a conductive member electrically connecting said projection and said pad,

wherein a region of said substrate where the projection is formed is deformed more easily than a region apart therefrom; and further comprising:

a second plate member arranged so as to oppose to the surface of said substrate where the pad is formed, and provided with a wire electrically communicated with said pad; and

a third plate member arranged between said substrate and said second plate member,

wherein said third plate member is formed of a material having a Young's modulus of 60 GPa or more, and has a thickness of 100 μm or more.

8. A test apparatus of a semiconductor apparatus, comprising:

a substrate provided with a projection formed on one main surface of said substrate so as to be electrically connectable to an electrode of a tested semiconductor apparatus, wherein said substrate is made of silicon;

a pad formed on a back surface side of said one main surface; and

a conductive member electrically connecting said projection and said pad,

wherein a region of said substrate where the projection is formed is deformed more easily than a region apart therefrom; and

further comprising:

a second plate member arranged so as to oppose to the surface of said substrate where the pad is formed, and provided with a wire electrically communicated with said pad; and

a third plate member arranged between said substrate and said second plate member,

wherein said third plate member is formed of a material having a Young's modulus of 60 GPa or more, and has a thickness of 100 μm or more.

9. A test apparatus of a semiconductor apparatus according to claim 8 , wherein said projection and said third plate member are arranged via a space.

10. A test apparatus of a semiconductor apparatus, comprising:

a substrate provided with a projection formed on one main surface of said substrate so as to be electrically connectable to an electrode of a tested semiconductor apparatus, wherein said substrate is made of silicon;

a pad formed on a back surface side of said one main surface; and

a conductive member electrically connecting said projection and said pad,

wherein a region of said substrate where the projection is formed is deformed more easily than a region apart therefrom, and

wherein a plurality of said substrates are provided substantially within one surface.

11. A test apparatus of a semiconductor apparatus, comprising:

a substrate provided with a projection formed on one main surface of said substrate so as to be electrically connectable to an electrode of a tested semiconductor apparatus, wherein said substrate is made of silicon, and wherein said projection is made of silicon integrated with said substrate, and has a conductive coat thereon;

a pad formed on a back surface side of said one main surface; and

a conductive member electrically connecting said projection and said pad,

wherein a region of said substrate where the projection is formed is deformed more easily than a region apart therefrom.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER/CHANGE OF NAME Recorded Aug 31, 2011
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 026837/0505 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2003
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORPORATION
Reel/Frame 014569/0585 →
Priority Claims (1)
JP 10-069786 · Mar 19, 1998 · national
Continuity (2)
Continuation 0964651100
Related Publication 20030092206A1 · May 15, 2003