Wide-range programmable delay line

1. An apparatus comprising:

an input section configured to present a first intermediate signal by selecting (i) an input clock signal when said apparatus is in input mode and (ii) a feedback of an output signal when said apparatus is in a feedback mode;

a first delay circuit configured to generate a second intermediate signal by delaying said first intermediate signal by inserting a first delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay; and

a second delay circuit configured to generate said output signal by delaying said second intermediate signal by inserting a second delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.

2. The apparatus according to claim 1 , wherein said first delay circuit comprises a coarse delay circuit configured to generate a substantial amount of delay to allow for the die size of said apparatus to be reduced.

3. The apparatus according to claim 1 , wherein said second delay circuit comprises a fine delay circuit configured to provide precision delay for said apparatus.

4. The apparatus according to claim 1 , wherein said first delay circuit comprises a plurality of coarse delay elements presented to a multiplexer, wherein said multiplexer selects one of said coarse delay elements in response to said first control signal.

5. The apparatus according to claim 1 , further comprising:

a plurality of first delay circuits, each configured to add one or a plurality of delays.

6. The apparatus according to claim 1 , wherein (i) said second delay comprises one or more fine delay increments and (ii) a delay difference between said first delay circuit and said second delay circuit is less than said one fine delay increment.

7. The apparatus according to claim 6 , wherein said delay difference is equal to said one fixed increment minus a total of said one or more fine delay increments.

8. The apparatus according to claim 1 , wherein said input section is configured to receive a clock enable signal to control the selection between said input clock signal and said feedback of an output signal.

9. The apparatus according to claim 8 , wherein said input section comprises a multiplexer configured to select between said input clock signal and said feedback of an output in response to said clock enable signal.

10. An apparatus comprising:

means for presenting a first intermediate signal by selecting (i) an input clock signal when said apparatus is in an input mode and (ii) a feedback of an output signal when said apparatus is in a feedback mode;

means for generating a second intermediate signal by delaying said first intermediate signal by inserting a fixed delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay; and

means for generating said output signal by delaying said second intermediate signal by inserting a second delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.

11. A method for implementing a programmable delay comprising the steps of:

(A) presenting a first intermediate signal by selecting (i) an input clock signal when in an input mode and (ii) a feedback of an output signal when in a feedback mode;

(B) generating a second intermediate signal with a first delay circuit by delaying said first intermediate signal by inserting a first delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay; and

(C) generating said output signal with a second delay circuit by delaying said second intermediate signal by inserting a programmable delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.

12. The method according to claim 11 , wherein step (B) implements a coarse delay to generate a substantial amount of delay and allow for a reduction of die size.

13. The method according to claim 11 , wherein step (C) implements a fine delay circuit to provide precision delay.

14. The method according to claim 11 , wherein step (B) is implemented with a plurality of coarse delay elements presented to a multiplexer, wherein said multiplexer selects one of said coarse delay elements in response to said first control signal.

15. The method according to claim 11 , wherein said method is implemented in a memory interface.

16. The method according to claim 11 , wherein said method is implemented in a double data rate memory interface.

17. The method according to claim 11 , wherein (i) said second delay comprises one or more fine delay increments and (ii) a delay difference between said first delay circuit and said second delay circuit is less than said one fine delay increment.

18. The method according to claim 17 , wherein said delay difference is equal to said one fixed increment minus a total of said one or more fine delay increments.

19. The method according to claim 11 , wherein step (A) further comprises the step of:

receiving a clock enable signal to select between said input clock signal and said feedback of an output signal.

20. The method according to claim 19 , further comprising the step of:

presenting said clock enable signal to a multiplexer to select between said input clock signal and said feedback of an output signal.