IP Library › Granted Patent US 7,135,259
Granted Patent B2
US 7,135,259 · App. 10/447,010 · Granted Nov 14, 2006

Scatterometric method of monitoring hot plate temperature and facilitating critical dimension control

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
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Quick Facts
Patent No.
US 7,135,259
App. No.
10/447,010
Granted
Nov 14, 2006
Kind
B2
Abstract

A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

Claims (38)

1. A method of determining temperatures at localized regions of a substrate during processing of said substrate in a photolithography process, comprising the following steps:

independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on said substrate with a light source, so that light is diffracted off said plurality of locations of said photoresist pattern;

measuring said diffracted light from said plurality of locations to determine measured diffracted values associated with respective locations from said plurality of locations; and

comparing said measured diffracted values against a library correlating diffracted values to respective processing temperatures of said photoresist layer; and

from said comparison, determining a pre-illumination processing temperature distribution, said distribution comprising processing temperatures for said respective locations from said plurality of locations.

2. The method of claim 1 , wherein said photoresist pattern is a latent image pattern.

3. The method of claim 1 , wherein said photoresist pattern is a developed photoresist pattern.

4. A method of processing semiconductor substrates, comprising the following steps:

forming a photoresist layer including a photoresist pattern over a substrate, said forming step including at least one baking step;

independently illuminating said photoresist pattern at a plurality of locations on said substrate with a light source, so that light is diffracted off said plurality of locations of said photoresist pattern;

measuring said diffracted light from said plurality of locations using scatterometry techniques to determine measured diffracted values associated with respective locations from said plurality of locations; and

comparing said measured diffracted values against a library correlating diffracted values to respective processing temperatures of said photoresist layer during said at least one baking step; and

from said comparison, determining a processing temperature distribution, said distribution comprising processing temperatures during said at least one baking step for said respective locations from said plurality of locations.

5. The method of claim 4 , further comprising the step of controlling a heater used in said at least one baking step based on said processing temperature distribution.

6. The method of claim 5 , wherein said controlling step includes the step of adjusting at least one heating element in said heater to provide substantially uniform heating of a photoresist layer at said plurality of locations on subsequently processed substrates.

7. The method of claim 5 , wherein said at least one baking step includes a post-exposure baking step.

8. The method of claim 5 , wherein said at least one baking step includes a pre-exposure baking step.

9. The method of claim 4 , wherein said library includes data associating photoresist pattern profiles with respective processing temperatures.

10. The method of claim 4 , wherein said photoresist pattern is a latent image pattern.

11. The method of claim 4 , wherein said photoresist pattern is a developed photoresist pattern.

12. The method of claim 4 , wherein said at least one baking step comprises heating said substrate with a heater including a plurality of spaced heating elements, said method further comprising adjusting at least one heating element from said plurality of spaced heating elements based on results of said comparison to provide substantially uniform heating of a photoresist layer at said plurality of locations.

13. A method of processing semiconductor substrates, comprising the following steps:

forming a photoresist layer including a photoresist pattern over a substrate, said forming step including at least one baking step;

independently illuminating said photoresist pattern at a plurality of locations on said substrate with a light source, so that light is diffracted off said plurality of locations of said photoresist pattern;

measuring said diffracted light from said plurality of locations using scatterometry techniques to determine measured diffracted values associated with respective locations from said plurality of locations;

comparing said measured diffracted values against a library correlating diffracted values to respective processing temperatures of said photoresist layer during said at least one baking step, said library including data associating photoresist pattern profiles with respective processing temperatures;

from said comparison, determining a processing temperature distribution, said distribution comprising processing temperatures during said at least one baking step for said respective locations from said plurality of locations; and

controlling a heater used in said at least one baking step based on said processing temperature distribution.

14. The method of claim 13 , wherein said controlling step includes the step of adjusting at least one heating element in said heater to provide substantially uniform heating of a photoresist layer at said plurality of locations on subsequently processed substrates.

15. The method of claim 13 ,

wherein said forming step includes a pre-exposure baking step and a post-exposure baking step,

wherein said illuminating step occurs before said post-exposure baking step; and

wherein said controlling step includes the step of adjusting at least one heating element in a heater used in said post-exposure baking step.

16. The method of claim 13 , wherein said at least one baking step includes a post-exposure baking step.

17. The method of claim 13 , wherein said at least one baking step includes a pre-exposure baking step.

18. The method of claim 13 , wherein said photoresist pattern is a latent image pattern.

19. The method of claim 13 , wherein said photoresist pattern is a developed photoresist pattern.

20. The method of claim 13 , wherein said heater includes a plurality of spaced heating elements, wherein said controlling step includes the step of adjusting at least one heating element from said plurality of spaced heating elements based on results of said comparison to provide substantially uniform heating of a photoresist layer at said plurality of locations.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2003
From: CHEN, LI-JUI; KE, CHIH-MING; HO, BANG-CHING; SHIH, JEN-CHIEH; GAU, TSAI-SHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 014123/0742 →
Continuity (1)
Related Publication 20040241561A1 · Dec 2, 2004