Adaptive radio transceiver with noise suppression

Assignee: Broadcom Corporation

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Quick Facts

Patent No.: US 7,136,622
App. No.: 11/110,349
Granted: Nov 14, 2006
Kind: B2

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Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims (74)

1. A single integrated circuit chip in a wireless transceiver, comprising:

a logic circuit having a power input and a power return;

a capacitor operatively coupled across the power input and the power return;

a first resistor having a first end operatively coupled to the power input and a second end operatively coupled to a power source; and

a second resistor having a first end operatively coupled to the power return and a second cad operatively coupled to a power source return.

2. The single integrated circuit chip according to claim 1 , wherein the logic circuit comprises a differential circuit.

3. The single integrated circuit chip according to claim 2 , wherein the differential circuit comprises a first logic gate and a second logic gate.

4. The single integrated circuit chip according to claim 3 , wherein the first logic gate and the second logic gate are of the same type of gate.

5. The single integrated circuit chip according to claim 4 ,

wherein the first logic gate comprises a first inverter, and

wherein the second logic gate comprises a second inverter.

6. The single integrated circuit chip according to claim 5 ,

wherein the first inverter comprises a first CMOS inverter, and

wherein the second inverter comprises a second CMOS inverter.

7. The single integrated circuit chip according to claim 6 ,

wherein the first CMOS inverter comprises a p-channel transistor and an n-channel transistor.

wherein the p-channel transistor has a source, a gate and a drain, the source of the p-channel transistor being operatively coupled to the power input, and

wherein the n-channel transistor has a source, a gate and a drain, the source of the n-channel transistor being operatively coupled to the power return, the gate of the n-channel transistor being operatively coupled to the gate of the p-channel transistor to form an input node, the drain of the n-channel transistor being operatively coupled to the drain of the p-channel transistor to form an output node.

8. The single integrated circuit chip according to claim 7 , wherein the differential circuit has a differential input and a differential output, the differential input comprising the input node for the first CMOS inverter, the differential output comprising the output node for the first CMOS inverter.

9. The singe integrated circuit chip according to claim 1 , wherein the wireless transceiver is a mobile wireless transceiver.

10. The single integrated circuit chip according to claim 1 ,

wherein the logic circuit comprises a differential circuit wit diferential inputs, and

wherein the capacitor circulates charge during an input transition at the differential inputs.

11. The singe integrated circuit chip according to claim 10 , wherein the capacitor is adapted to reduce noise in the logic circuit.

12. The singe integrated circuit chip according to claim 1 , wherein the logic circuit, the capacitor, the first resistor and the second resistor are part of a fully balanced circuit.

13. The single integrated circuit chip according to claim 12 , wherein the fully balanced circuit utilizes common mode averaging.

14. The single integrated circuit chip according to claim 12 , wherein the fully balanced circuit isolates the capacitor from the power source.

15. The single integrated circuit chip according to claim 12 , wherein the fully balanced circuit reduces noise generated by periodic signals.

16. The single integrated circuit chip according to claim 12 , wherein the fully balanced circuit reduces noise generated by non-periodic signals.

17. The single integrated circuit chip according to claim 12 , wherein the fully balanced circuit reduces spurious noise.

18. The single integrated circuit chip according to claim 1 , wherein the capacitor can be charged via the first resistor or the second resistor.

19. The single integrated circuit chip according to claim 1 ,

wherein the first end of the first resistor is operatively coupled to a first end of the capacitor, and

wherein the first end of the second resistor is operatively coupled to a second end of the capacitor.

20. The single integrated circuit chip according to claim 1 , wherein the wireless transceiver is part of a wireless local area network.

21. The single integrated circuit chip according to claim 1 , wherein the wireless transceiver is part of an RF communications network.

22. The single integrated circuit chip according to claim 1 , wherein the single integrated circuit chip utilizes CMOS technology.

23. The single integrated circuit chip according to claim 1 ,