Dual-channel CMOS transistors with differentially strained channels
A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.
1. A semiconductor structure comprising:
a surface layer comprising strained silicon disposed over a substrate, the surface layer including a first region having a non-zero first thickness and a second region having a second thickness, the first region having a bottom boundary co-planar with a bottom boundary of the second region and the first thickness being less than the second thickness;
a first source and a first drain in the first region, the first source and the first drain including a first type of dopant; and
a second source and a second drain in the second region, the second source and the second drain including a second type of dopant,
wherein the substrate comprises a region under compressive strain sharing an interface with the surface layer, the strained surface layer enhancing mobility of electrons and the compressively strained substrate region enhancing mobility of holes.
2. The structure of claim 1 further comprising:
an underlying relaxed layer.
3. The structure of claim 2 , wherein the underlying relaxed layer comprises germanium.
4. The structure of claim 2 , wherein the underlying relaxed layer comprises silicon.
5. The structure of claim 1 further comprising:
an insulator layer,
wherein the surface layer is disposed over the insulator layer.
6. The structure of claim 1 , wherein the surface layer comprises tensilely strained silicon.
7. The structure of claim 1 , wherein the first type of dopant is p-type and the second type of dopant is n-type.
8. The structure of claim 1 , wherein the first type of dopant is n-type and the second type of dopant is p-type.
9. The structure of claim 1 further comprising:
a gate disposed above the surface layer, the first thickness being sufficiently small such that application of an operating voltage to the gate modulates movement of a plurality of charge carriers within the compressively strained substrate region and a majority of the carriers populate the compressively strained substrate region.
10. The structure of claim 9 further comprising:
an insulator between the gate and the surface layer.
11. The structure of claim 1 , wherein the compressively strained substrate region comprises silicon.
12. The structure of claim 1 , wherein the compressively strained substrate region comprises germanium.
13. The structure of claim 1 , wherein the first thickness is greater than 7 Å.
14. The structure of claim 1 , further comprising:
a gate dielectric disposed over a portion of at least the first region of the surface layer.
15. The structure of claim 14 , wherein the gate dielectric layer comprises silicon dioxide.
16. The structure of claim 14 , wherein the gate dielectric layer is disposed over a portion of the second region of the surface layer.
17. The structure of claim 14 , wherein the gate dielectric layer has a thickness of approximately 10–100 Å.
18. The structure of claim 17 , wherein the first thickness is approximately 7–20 Å.
19. The structure of claim 18 , wherein the first thickness is less than 10 Å.
20. The structure of claim 17 , wherein the gate dielectric layer has a thickness of approximately 15 Å.
21. The structure of claim 20 , wherein the first thickness is less than 10Å.