Decoupling circuit for co-packaged semiconductor devices
A model for noise coupling in copackaged semiconductor devices due to coupling through parasitic impedances, and a method and decoupling circuit to minimize the effects of such noise. In one example, which is not intended to be limiting either as to the application of the invention or its implementation, a decoupling circuit for a power factor correction IC co-packaged with a power transistor such as an IGBT or MOSFET includes a first branch formed by a capacitor and a parallel branch formed by a resistor and a capacitor in series. The circuit, which is part of the IC, is connected between a power supply node and the circuit ground and, at frequencies associated with the noise, exhibits low impedance to the ground, and a high impedance to the IC and the transistor.
1. A semiconductor device comprising:
at least two separate circuit units co-packaged with an insulating material between the units, and coupled together through parasitic impedance associated with the first unit, wherein the first unit is susceptible to noise generated by the second unit which is coupled through the parasitic impedance and the insulating material; and
a decoupling circuit between the first and second units connected to a ground connection node of the first unit and a power supply node of the first unit.
2. A semiconductor device as described in claim 1 , wherein the decoupling circuit exhibits a high impedance between the power supply node and the functional elements of the first and second units at frequencies associated with the noise, and a low impedance to the ground connection node from the power supply input node at the frequencies associated with the noise.
3. A semiconductor device as described in claim 1 , wherein the decoupling circuit comprises a first branch formed by a capacitor and a second branch in parallel with the first branch formed by a resistor and a capacitor in series.
4. A semiconductor device comprising:
a power transistor;
an integrated circuit which provides a signal to a control terminal of the power transistor,
the integrated circuit and the power transistor being co-packaged;
and a decoupling circuit connected between a power supply node of the integrated circuit and a ground connection node of the integrated circuit,
the decoupling circuit being configured and constructed to minimize the effect on the integrated circuit of switching noise generated by the power transistor.
5. A semiconductor device as described in claim 4 , wherein the decoupling circuit exhibits a high impedance between the power supply node and the power transistor, and between the power supply node and the functional elements of this integrated circuit at frequencies associated wit the noise, and a low impedance to a ground connection node of the integrated circuit from the power supply node at the frequencies associated with the noise.
6. A semiconductor device as described in claim 4 , wherein the decoupling circuit comprises a first branch formed by a capacitor and a second branch in parallel with the first branch formed by a resistor and a capacitor in series.
7. A method of reducing noise in a semiconductor device comprising at least two separate circuit units co-packaged with an insulating material between the units, and coupled together through parasitic impedance associated with the first unit, wherein the first unit is susceptible to noise generated by the second unit which is coupled through the parasitic impedance and the insulating material the method comprising the steps of:
modeling a noise coupling mechanism between the second and first units based on the behavior of the parasitic impedance and the insulating material;
designing a decoupling circuit in accordance with the coupling mechanism defined by the model to block transmission of signals at frequencies associated with the noise; and
connecting the decoupling circuit between the first and second circuit units.
8. A method as described in claim 7 , wherein the decoupling circuit is designed to present high impedance at a power supply node of the first unit and a low impedance bypass to a ground connection node of the first unit.
9. A method as described in claim 7 , wherein the decoupling circuit comprises a first branch formed by a capacitor and a second branch in parallel with the first branch formed by a resistor and a capacitor in series.
10. A method as described in claim 9 , wherein the decoupling circuit is connected between a power supply node of the first unit and a ground connection node of the first unit.