Wafer level semiconductor package with build-up layer and method for fabricating the same
View Patent ↗A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
1. A wafer level semiconductor package with a build-up layer, comprising:
a rigid frame having a through hole;
at least a chip received in the through hole of the rigid frame, the chip being thinner than the rigid frame by 0.05 mm to 0.5 mm, wherein a space is formed between the chip and the rigid frame;
a low-modulus buffer material filled in the space between the chip and the rigid frame;
a build-up layer formed on the rigid frame and the chip such that the build-up layer is electrically connected to the chip; and
a plurality of conductive elements being electrically connected to the build-up layer such that the chip is electrically connected to external devices.
2. The wafer level semiconductor package with a build-up layer of claim 1 , wherein a thickness of the rigid frame is the same as that of the chip.
3. The wafer level semiconductor package with a build-up layer of claim 1 , wherein a thickness difference between the rigid frame and the chip is more preferably to be 0.1 mm.
4. The wafer level semiconductor package with a build-up layer of claim 1 , wherein an inactive surface of the chip is exposed in atmosphere.
5. The wafer level semiconductor package with a build-up layer of claim 4 , wherein a heat sink is further provided to be attached to the inactive surface of the chip.
6. The wafer level semiconductor package with a build-up layer of claim 1 , wherein an inactive surface of the chip is covered by the low-modulus buffer material.
7. The wafer level semiconductor package with a build-up layer of claim 1 , wherein the through hole is rectangular.
8. The wafer level semiconductor package with a build-up layer of claim 7 , wherein a corner of the through hole is rounded.
9. The wafer level semiconductor package with a build-up layer of claim 1 , wherein the rigid frame is made of a material selected from the group consisting of glass, metal and thermosetting materials.
10. The wafer level semiconductor package with a build-up layer of claim 1 , wherein the low-modulus buffer material is selected from the group consisting of silica gel, epoxy resins and polyimide resins.
11. The wafer level semiconductor package with a build-up layer of claim 1 , wherein the conductive element is a solder ball.