IP Library › Granted Patent US 7,183,137
Granted Patent B2
US 7,183,137 · App. 10/725,697 · Granted Feb 27, 2007

Method for dicing semiconductor wafers

Assignee: Taiwan Semiconductor Manufacturing Company
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Quick Facts
Patent No.
US 7,183,137
App. No.
10/725,697
Granted
Feb 27, 2007
Kind
B2
Abstract

A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.

Claims (24)

1. A method for dicing a wafer having a base material with a diamond structure, the method comprising:

forming one or more dies with at least one edge thereof at an offset angle from a natural cleavage direction of the diamond structure with one or more protection elements along at least one dicing line; and

dicing the wafer along the dicing line,

wherein the protection elements protect the dies from undesired cracking while the wafer is being diced along the dicing line, the protection elements being one of metal based elements formed on the wafer and dielectric elements formed on the wafer.

2. A method for dicing a wafer having a base material with a diamond structure, the method comprising:

forming one or more dies with at least one edge thereof at an offset angle from a natural cleavage direction of the diamond structure with one or more protection elements along at least one dicing line; and

dicing the wafer along the dicing line,

wherein the protection elements protect the dies from undesired cracking while the wafer is being diced along the dicing line and comprise one or more recesses formed into the wafer that are substantially leveled with a top surface of a die formed on the wafer.

3. A method for dicing a wafer having a base material with a diamond structure, the method comprising:

forming one or more dies with at least one edge thereof at an offset angle from a natural cleavage direction of the diamond structure with one or more protection elements along at least one dicing line; and

dicing the wafer along the dicing line,

wherein the protection elements protect the dies from undesired cracking while the wafer is being diced along the dicing line and comprise one or more recesses formed into the wafer, the recesses are filled with one or more organic materials for absorbing stress caused during the dicing.

4. The method of claim 1 wherein the die further includes one or more protection elements at one or more predetermined locations on its periphery.

5. The method of claim 1 wherein the protection elements on the periphery are unconnected from a core circuitry of the die.

6. The method of claim 1 wherein the wafer is a {110} wafer and the natural cleavage direction is the < 100 > direction.

7. The method of claim 1 wherein the wafer is a {100} wafer and the natural cleavage direction is the < 110 > direction.

8. The method of claim 2 wherein the die further includes one or more protection elements at one or more predetermined locations on its periphery.

9. The method of claim 2 wherein the protection elements on the periphery are unconnected from a core circuitry of the die.

10. The method of claim 2 wherein the wafer is a {110} wafer and the natural cleavage direction is the < 100 > direction.

11. The method of claim 2 wherein the wafer is a {100} wafer and the natural cleavage direction is the < 110 > direction.

12. The method of claim 3 wherein the die further includes one or more protection elements at one or more predetermined locations on its periphery.

13. The method of claim 3 wherein the protection elements on the periphery are unconnected from a core circuitry or the die.

14. The method of claim 3 wherein the wafer is a {110} wafer and the natural cleavage direction is the < 100 > direction.

15. The method of claim 3 wherein the wafer is a {100} wafer and the natural cleavage direction is the < 110 > direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2004
From: LEE, HSIN-HUI; HUANG, CHIEN-CHAO; WANG, CHAO-HSIUNG; YANG, FU-LIANG; HU, CHENMING
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
Reel/Frame 015149/0729 →
Continuity (1)
Related Publication 20050118790A1 · Jun 2, 2005